View Z8F0811_1647702.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

product specification z8f082x/z8f081x/z8f042x/ z8f041x z8 encore! ? z8f082x series microcontrollers with flash memory and 10-bit a/d converter preliminary ps019707-1003 ( datasheet : )
ps019707-1003 p r e l i m i n a r y disclaimer this publication is subject to replacement by a later edition. to determine whether a later edition exists, or to reques t copies of publications, contact: zilog worldwide headquarters 532 race street san jose, ca 95126 telephone: 408.558.8500 fax: 408.558.8300 www.zilog.com document disclaimer zilog is a registered trademark of zilog inc. in th e united states and in other countries. all other products and/or service names mentioned herein may be trademarks of the companies with which they are associated. ?2003 by zilog, inc. all rights reserved. information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. zilog, inc. does not assume liability for or provide a representation of accuracy of the information, devices, or technology described in this document. zilog also does not assume liability for intellectual property infringement related in any manner to use of information, devices, or technology described herein or otherwise. devices sold by zilog, inc. are covered by warranty and limitation of liability provisions a ppearing in the zilog, inc. terms and conditions of sale. zilog, inc. makes no warranty of merchantabi lity or fitness for any purpose except with the express written approval of zilog, use of informati on, devices, or technology as critical components of life support systems is not authorized. no licens es are conveyed, implicitly or otherwise, by this document under any intellectual property rights.
ps019707-1003 p r e l i m i n a r y table of contents z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? iii table of contents introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 part selection guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 cpu and peripheral overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ez8 cpu features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 general purpose i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 flash controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 10-bit analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 uart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 i 2 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 reset controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 on-chip debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 signal and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 available packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 pin configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 register file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 flash information area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 register file address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 contol register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 reset and stop mode recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 reset types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 voltage brown-out reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
ps019707-1003 p r e l i m i n a r y table of contents z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? iv watch-dog timer reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 external pin reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 stop mode recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 stop mode recovery using watch-dog timer time-out . . . . . . . . . . . . . . . . . . 33 stop mode recovery using a gpio port pin transition . . . . . . . . . . . . . . . . . . . . 34 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 general-purpose i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 gpio port availability by device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 gpio alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 gpio interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 gpio control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 port a-c address registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 port a-c control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 port a-c input data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 port a-c output data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 interrupt vector listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 master interrupt enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 interrupt vectors and priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 interrupt assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 software interrupt assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 interrupt control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 interrupt request 0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 interrupt request 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 interrupt request 2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 irq0 enable high and low bit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 irq1 enable high and low bit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 irq2 enable high and low bit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 interrupt edge select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 interrupt control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
ps019707-1003 p r e l i m i n a r y table of contents z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? v operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 timer operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 reading the timer count values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 timer output signal operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 timer control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 timer 0-1 high and low byte registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 timer reload high and low byte registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 timer 0-1 pwm high and low byte registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 timer 0-1 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 watch-dog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 watch-dog timer refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 watch-dog timer time-out response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 watch-dog timer reload unlock sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 watch-dog timer control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 watch-dog timer control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 watch-dog timer reload upper, high and low by te registers . . . . . . . . . . . . . . 79 uart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 transmitting data using the polled method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 transmitting data using the interrupt-driven method . . . . . . . . . . . . . . . . . . . . . . . 84 receiving data using the polled method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 receiving data using the interrupt -driven method . . . . . . . . . . . . . . . . . . . . . . . . . 85 clear to send (cts) operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 multiprocessor (9-bit) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 external driver enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 uart interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 uart baud rate generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 uart control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 uart transmit data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 uart receive data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 uart status 0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 uart status 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 uart control 0 and control 1 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 uart address compare register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 uart baud rate high and low byte registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
ps019707-1003 p r e l i m i n a r y table of contents z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? vi infrared encoder/decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 transmitting irda data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 receiving irda data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 infrared encoder/decoder control register definitions . . . . . . . . . . . . . . . . . . . . . . . . 106 serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 spi signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 spi clock phase and polarity control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 multi-master operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 slave operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 spi interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 spi baud rate generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 spi control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 spi data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 spi control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 spi status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 spi mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 spi diagnostic state register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 spi baud rate high and low byte registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 i2c controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 sda and scl signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 i 2 c interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 write transaction with a 7-bit address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 write transaction with a 10-bit address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 read transaction with a 7-bit address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 read transaction with a 10-bit address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 i2c control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 i2c data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 i2c status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 i2c control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 i2c baud rate high and low byte registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
ps019707-1003 p r e l i m i n a r y table of contents z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? vii i2c diagnostic state register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 i2c diagnostic control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 automatic power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 single-shot conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 continuous conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 adc control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 adc control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 adc data high byte register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 adc data low bits register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 information area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 0 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 timing using the flash frequency registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 flash read protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 flash write/erase protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 byte programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 page erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 mass erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 flash controller bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 flash controller behavior in debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 flash control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 flash control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 flash status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 flash page select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 flash sector protect register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 flash frequency high and low byte registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 option bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 option bit configuration by reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 option bit address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 program memory address 0000h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 program memory address 0001h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 on-chip debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
ps019707-1003 p r e l i m i n a r y table of contents z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? viii operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 ocd interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 ocd data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 ocd auto-baud detector/generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 ocd serial errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 ocdcntr register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 on-chip debugger commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 on-chip debugger control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 ocd control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 ocd status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 on-chip oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 crystal oscillator operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 oscillator operation with an external rc network . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 71 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5 on-chip peripheral ac and dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 177 general purpose i/o port input da ta sample timing . . . . . . . . . . . . . . . . . . . . . . 180 general purpose i/o port output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 on-chip debugger timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 spi master mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 spi slave mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 i2c timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 uart timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 ez8 cpu instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8 assembly language programming introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 assembly language syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 ez8 cpu instruction notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 condition codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2 ez8 cpu instruction classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 ez8 cpu instruction summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 flags register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 opcode maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
ps019707-1003 p r e l i m i n a r y table of contents z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? ix ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 16 part number description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 precharacterization product . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 document information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 document number description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 customer feedback form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 the z8 encore! ? product specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 customer information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 product information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 return information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 problem description or suggestion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
ps019707-1003 p r e l i m i n a r y list of figures z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? x list of figures figure 1. z8 encore! ? block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 figure 2. z8f0821 and z8f0421 in 20-pin ssop an d pdip packages . . . . . . . . . . . . 7 figure 3. z8f0822 and z8f0422 in 28-pin soic and pdip packages . . . . . . . . . . . . 7 figure 4. Z8F0811 and z8f0411 in 20-pin ssop an d pdip packages . . . . . . . . . . . . 8 figure 5. z8f0812 and z8f0412 in 28-pin soic and pdip packages . . . . . . . . . . . . 8 figure 6. power-on reset operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 7. voltage brown-out reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 8. gpio port pin block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 9. interrupt controller block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 10. timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 11. uart block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 12. uart asynchronous data format without parity . . . . . . . . . . . . . . . . . . . 83 figure 13. uart asynchronous data format with pa rity . . . . . . . . . . . . . . . . . . . . . . 83 figure 14. uart asynchronous mu ltiprocessor mode data format . . . . . . . . . . . . . 87 figure 15. uart driver enable signal timing (shown with 1 stop bit and parity) . 89 figure 16. uart receiver interrupt service routine flow . . . . . . . . . . . . . . . . . . . . 91 figure 17. infrared data communi cation system block diagram . . . . . . . . . . . . . . 102 figure 18. infrared data transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 figure 19. infrared data reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 figure 20. spi configured as a master in a single master, single slave system . . . 107 figure 21. spi configured as a master in a single master, multiple slave system . . 108 figure 22. spi configured as a slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 figure 23. spi timing when phase is 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 figure 24. spi timing when phase is 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 figure 25. 7-bit addressed slave data transfer format . . . . . . . . . . . . . . . . . . . . . . 123 figure 26. 10-bit addressed slave data transfer format . . . . . . . . . . . . . . . . . . . . . 124 figure 27. receive data transfer format for a 7-bit addressed slave . . . . . . . . . . . 125 figure 28. receive data format for a 10-bit addressed slave . . . . . . . . . . . . . . . . . 126 figure 29. analog-to-digital conver ter block diagram . . . . . . . . . . . . . . . . . . . . . . 134 figure 30. flash memory arrangement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 figure 31. on-chip debugger block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
ps019707-1003 p r e l i m i n a r y list of figures z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? xi figure 32. interfacing the on-chip debugger?s dbg pin with an rs-232 interface (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 figure 33. interfacing the on-chip debugger?s dbg pin with an rs-232 interface (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 figure 34. ocd data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 figure 35. recommended 20mhz crystal oscillato r configuration . . . . . . . . . . . . . 168 figure 36. connecting the on-chip oscillator to an external rc network . . . . . . . . 169 figure 37. typical oscillator frequency as a function of the r and c values . . . . . 170 figure 38. icc versus system clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 figure 39. icc versus system clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 figure 40. port input sample timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 figure 41. gpio port output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 figure 42. on-chip debugger timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 figure 43. spi master mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 figure 44. spi slave mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 figure 45. i2c timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 figure 46. uart timing with cts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 figure 47. uart timing without cts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 figure 48. flags register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 figure 49. opcode map cell description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 figure 50. first opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 figure 51. second opcode map after 1fh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 figure 52. 20-pin small shrink outline package (ssop) . . . . . . . . . . . . . . . . . . . . . 212 figure 53. 20-pin plastic dual-inline package (pdip) . . . . . . . . . . . . . . . . . . . . . . . . 213 figure 54. 28-pin small outline integrated circu it package (soic) . . . . . . . . . . . . . 214 figure 55. 28-pin plastic dual-inline package (pdip) . . . . . . . . . . . . . . . . . . . . . . . . 215
ps019707-1003 p r e l i m i n a r y list of tables z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? xii list of tables table 1. z8f082x family part selection guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 table 2. z8f082x family package options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 3. signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 4. pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 5. z8f082x family program memory maps . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 6. z8f082x family information area map . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 7. register file address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 8. reset and stop mode recovery charact eristics and latency . . . . . . . . . . 29 table 9. reset sources and resulting reset type . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 10. stop mode recovery sources and resu lting action . . . . . . . . . . . . . . . . 33 table 11. port availability by device and package type . . . . . . . . . . . . . . . . . . . . . . 37 table 12. port alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 13. gpio port registers and sub-registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 14. port a-c gpio address registers (pxaddr) . . . . . . . . . . . . . . . . . . . . . . 40 table 15. port a-c control registers (pxctl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 16. port a-c data direction sub-registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 17. port a-c alternate function sub-registers . . . . . . . . . . . . . . . . . . . . . . . . 42 table 18. port a-c output control sub-registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 19. port a-c high drive enable sub-registers . . . . . . . . . . . . . . . . . . . . . . . . 44 table 20. port a-c stop mode recovery source enable sub-registers . . . . . . . . . 45 table 21. port a-c input data registers (pxin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 22. port a-c pull-up enable sub-registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 23. port a-c output data register (pxout) . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 24. interrupt vectors in order of priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 25. interrupt request 0 register (irq0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 26. interrupt request 2 register (irq2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 27. interrupt request 1 register (irq1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 28. irq0 enable and priority encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 29. irq0 enable high bit register (irq0enh) . . . . . . . . . . . . . . . . . . . . . . . 55 table 30. irq1 enable and priority encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 31. irq0 enable low bit register (irq0enl) . . . . . . . . . . . . . . . . . . . . . . . . 56 table 32. irq1 enable low bit register (irq1enl) . . . . . . . . . . . . . . . . . . . . . . . . 57 table 33. irq2 enable and priority encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
ps019707-1003 p r e l i m i n a r y list of tables z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? xiii table 34. irq1 enable high bit register (irq1enh) . . . . . . . . . . . . . . . . . . . . . . . 57 table 35. irq2 enable low bit register (irq2enl) . . . . . . . . . . . . . . . . . . . . . . . . 58 table 36. irq2 enable high bit register (irq2enh) . . . . . . . . . . . . . . . . . . . . . . . 58 table 37. interrupt edge select register (irqes) . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 38. interrupt control register (irqctl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 39. timer 0-1 high byte register (txh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 40. timer 0-1 low byte register (txl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 41. timer 0-1 reload high byte register (txrh) . . . . . . . . . . . . . . . . . . . . . . 71 table 42. timer 0-1 reload low byte register (txrl) . . . . . . . . . . . . . . . . . . . . . . . 71 table 43. timer 0-1 pwm high byte register (txpwmh) . . . . . . . . . . . . . . . . . . . 72 table 44. timer 0-1 pwm low byte register (txpwml) . . . . . . . . . . . . . . . . . . . . 72 table 45. timer 0-1 control register (txctl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 46. watch-dog timer approximate time-out delays . . . . . . . . . . . . . . . . . . . 76 table 47. watch-dog timer control register (wdtctl) . . . . . . . . . . . . . . . . . . . . 78 table 48. watch-dog timer reload upper byte re gister (wdtu) . . . . . . . . . . . . . 79 table 49. watch-dog timer reload high byte re gister (wdth) . . . . . . . . . . . . . . 80 table 50. watch-dog timer reload low byte regi ster (wdtl) . . . . . . . . . . . . . . . 80 table 51. uart transmit data register (u0txd) . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 52. uart receive data register (u0rxd) . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 53. uart status 0 register (u0stat0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 54. uart status 1 register (u0stat1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 55. uart control 0 register (u0ctl0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 56. uart control 1 register (u0ctl1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 57. uart address compare register (u0addr) . . . . . . . . . . . . . . . . . . . . . 98 table 58. uart baud rate high byte register (u0brh) . . . . . . . . . . . . . . . . . . . . 99 table 59. uart baud rate low byte register (u0brl) . . . . . . . . . . . . . . . . . . . . . 99 table 60. uart baud rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 table 61. spi clock phase (phase) and cloc k polarity (clkpol) operation . . . 110 table 62. spi data register (spidata) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 table 63. spi control register (spictl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 table 64. spi status register (spistat) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 table 65. spi mode register (spimode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 table 66. spi diagnostic state register (spidst) . . . . . . . . . . . . . . . . . . . . . . . . . . 119 table 67. spi baud rate high byte register (spibrh) . . . . . . . . . . . . . . . . . . . . . 120 table 68. spi baud rate low byte register (spibrl) . . . . . . . . . . . . . . . . . . . . . . 120 table 69. i2c data register (i2cdata) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
ps019707-1003 p r e l i m i n a r y list of tables z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? xiv table 70. i2c status register (i2cstat) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 table 71. i2c control register (i2cctl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 table 72. i2c baud rate high byte register (i2c brh) . . . . . . . . . . . . . . . . . . . . . 131 table 73. i2c baud rate low byte register (i2cbrl) . . . . . . . . . . . . . . . . . . . . . . 131 table 74. i2c diagnostic state register (i2cdst) . . . . . . . . . . . . . . . . . . . . . . . . . . 132 table 75. i2c diagnostic control register (i2cdiag) . . . . . . . . . . . . . . . . . . . . . . 132 table 76. adc control register (adcctl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 table 77. adc data high byte register (adcdh) . . . . . . . . . . . . . . . . . . . . . . . . . 137 table 78. adc data low bits register (adcdl) . . . . . . . . . . . . . . . . . . . . . . . . . . 138 table 79. flash memory configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 table 80. flash memory sector addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 table 81. z8f082x family information area map . . . . . . . . . . . . . . . . . . . . . . . . . . 141 table 82. flash control register (fctl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 table 83. flash status register (fstat) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 table 84. flash page select register (fps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 table 85. flash sector protect register (fprot) . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 table 86. flash frequency high byte register ( ffreqh) . . . . . . . . . . . . . . . . . . . 149 table 87. flash frequency low byte register (ffr eql) . . . . . . . . . . . . . . . . . . . . 149 table 88. option bits at program memory addre ss 0000h . . . . . . . . . . . . . . . . . . 151 table 89. options bits at program memory addr ess 0001h . . . . . . . . . . . . . . . . . . 152 table 90. ocd baud-rate limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 table 91. on-chip debugger commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 table 92. ocd control register (ocdctl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 table 93. ocd status register (ocdstat) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 table 94. recommended crystal oscillator spec ifications (20mhz operation) . . . 168 table 95. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 table 96. dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 table 97. ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 table 98. power-on reset and voltage br own-out electrical characteristics and timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 table 99. flash memory electrical characteristic s and timing . . . . . . . . . . . . . . . . 177 table 100. watch-dog timer electrical characteristics and timing . . . . . . . . . . . . . 178 table 101. analog-to-digital converter electrical characteristics and timing . . . . . 178 table 102. gpio port input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 table 103. gpio port output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 table 104. on-chip debugger timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
ps019707-1003 p r e l i m i n a r y list of tables z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? xv table 105. spi master mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 table 106. spi slave mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 table 107. i2c timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 table 108. uart timing with cts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 table 109. uart timing without cts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 table 110. assembly language syntax example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 189 table 111. assembly language syntax example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . 189 table 112. notational shorthand . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 table 113. additional symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 table 114. condition codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 table 115. arithmetic instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 table 116. bit manipulation instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 table 117. block transfer instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 table 118. cpu control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 table 119. load instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 table 120. logical instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 table 121. program control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 table 122. rotate and shift instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 table 123. ez8 cpu instruction summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 table 124. opcode map abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 table 125. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
ps019707-1003 p r e l i m i n a r y manual objectives z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? xvi manual objectives this product specification provides detailed operating in formation for the z8f082x, z8f081x, z8f042x, and z8f041x devices within the z8 encore! ? microcontroller (mcu) family of products. within this document, the z8f082x, z8f081x, z8f042x, and z8f041x are referred to collectively as z8 encore! ? or the z8f082x family unless specifi- cally stated otherwise. about this manual zilog recommends that the user read and un derstand everything in this manual before setting up and using the product. however, we recognize that there are different styles of learning. therefore, we have designed this pr oduct specification to be used either as a how to procedural manual or a refe rence guide to important data. intended audience this document is written for zilog custom ers who are experience d at working with microcontrollers, integrated circu its, or printed circuit assemblies. manual conventions the following assumptions and conventions are adopted to provide clarity and ease of use: courier typeface commands, code lines and fragments, bits, eq uations, hexadecimal addresses, and various executable items are distinguished from general text by the use of the courier typeface. where the use of the font is not indicated, as in the index, the name of the entity is pre- sented in upper case. ? example: flags[1] is smrf . hexadecimal values hexadecimal values are de signated by uppercase h suffix and appear in the courier typeface. ? example: r1 is set to f8h. brackets the square brackets, [ ], indicate a register or bus. ? example: for the register r1[7:0], r1 is an 8-bit register, r1[7] is the most significant bit, and r1[0] is the least significant bit.
ps019707-1003 p r e l i m i n a r y manual objectives z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? xvii braces the curly braces, { }, indicate a single register or bus created by concatenating some com- bination of smaller registers, buses, or individual bits. ? example: the 12-bit register address { 0h , rp[7:4], r1[3:0]} is composed of a 4-bit hexadecimal value ( 0h ) and two 4-bit register values taken from the register pointer (rp) and working register r1. 0h is the most significant ni bble (4-bit value) of the 12-bit register, and r1[3:0] is the least significant nibble of the 12-bit register. parentheses the parentheses, ( ), indicate an indirect register address lookup. ? example: (r1) is the memory location referenced by th e address contained in the working register r1. parentheses/bracket combinations the parentheses, ( ), indicate an indirect regi ster address lookup and the square brackets, [ ], indicate a register or bus. ? example: assume pc[15:0] contains the value 1234h . (pc[15:0]) then refers to the contents of the memory location at address 1234h . use of the words set , reset and clear the word set implies that a register bit or a cond ition contains a logical 1. the words re set or clear imply that a register bit or a condition co ntains a logical 0. when either of these terms is followed by a number, the word logical may not be included; however, it is implied. notation for bits and similar registers a field of bits within a register is designated as: register[ n : n ]. ? example: addr[15:0] refers to bits 15 through bit 0 of the address. use of the terms lsb , msb , lsb , and msb in this document, the terms lsb and msb, when appearing in upper case, mean least sig- nificant byte and most significant byte , respectively. the lowercase forms, lsb and msb , mean least significant bit and most significant bit , respectively. use of initial uppercase letters initial uppercase letters designate settin gs and conditions in general text. ? example 1: the receiver fo rces the scl line to low. ? example 2: the master can generate a stop condition to abort the transfer.
ps019707-1003 p r e l i m i n a r y manual objectives z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? xviii use of all uppercase letters the use of all uppercase letters designates the names of states, modes, and commands. ? example 1: the bus is considered busy after the start condition. ? example 2: a start command triggers the processing of the initialization sequence. ? example 3: stop mode. bit numbering bits are numbered from 0 to n?1 where n indicates the total number of bits. for example, the 8 bits of a register are numbered from 0 to 7. safeguards it is important that all users understand the following safety terms, which are defined here. indicates a procedure or file may become corrupted if the user does not fol- low directions. trademarks zilog, ez8, z8 encore!, and z8 are trademarks of zilog, inc. in the u.s.a. and other countries. all other trademarks are the pr operty of their respective corporations. caution:
z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? ps019707-1003 p r e l i m i n a r y introduction 1 introduction the z8 encore! ? mcu family of products are the firs t in a line of zilog microcontroller products based upon the new 8-bit ez8 cpu. the z8f082x/z8f081x/z8f042x/z8f041x products, hereafter referred to collectively as the z8f082x family, expand upon zilog?s extensive line of 8-bit microcontrollers. the flash in-circuit pr ogramming capability allows for faster development time and progra m changes in the field.the new ez8 cpu is upward compatible with existing z8 ? instructions. the rich peripheral set of the z8 encore! ? makes it suitable for a variety of applica tions including motor control, security systems, home appliances, person al electronic devices, and sensors. features ? ez8 cpu ? up to 8kb flash memory with in-circuit programming capability ? 1kb register ram ? optional 2- to 5-channel, 10-bit analog-to-digital converter (adc) ? full-duplex uart ? i 2 c ? serial peripheral interface (spi) ? infrared data association (irda)-com pliant infrared encoder/decoders ? two 16-bit timers with capture, compare, and pwm capability ? watch-dog timer (wdt) with internal rc oscillator ? 11-19 i/o pins depending upon package ? programmable priority interrupts ? on-chip debugger ? voltage brown-out protection (vbo) ? power-on reset (por) ? 2.7-3.6v operating voltage with 5v-tolerant inputs ? 0 to +70c standard temperature and -40 to +105c extended temperature operating ranges
ps019707-1003 p r e l i m i n a r y introduction z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 2 part selection guide table 1 identifies the basic features and pack age styles available for each device within the z8f082x family product line. table 1. z8f082x family part selection guide part number flash (kb) ram (kb) i/o 16-bit timers with pwm adc inputs uarts with irda i 2 cspi package pin counts 20 28 z8f0822 8 1 19 2 5 1 1 1 x z8f0821 8 1 11 2 2 1 1 x z8f0812 8 1 19 2 0 1 1 1 x Z8F0811 8 1 11 2 0 1 1 x z8f0422 4 1 19 2 5 1 1 1 x z8f0421 4 1 11 2 2 1 1 x z8f0412 4 1 19 2 0 1 1 1 x z8f0411 4 1 11 2 0 1 1 x
ps019707-1003 p r e l i m i n a r y introduction z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 3 block diagram figure 1 illustrates the block diagram of the architecture of the z8 f082x family devices . figure 1. z8 encore! ? block diagram gpio irda uart i 2 c timers spi adc flash flash controller ram ram controller memory interrupt controller on-chip debugger ez8 cpu wdt with rc oscillator por/vbo & reset controller crystal oscillator register bus memory busses system clock
ps019707-1003 p r e l i m i n a r y introduction z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 4 cpu and peripheral overview ez8 cpu features the ez8, zilog?s latest 8-bit central pro cessing unit (cpu), meets the continuing demand for faster and more code-efficient microcontrollers. the ez8 cpu executes a superset of the original z8 ? instruction set. the ez8 cpu features include: ? direct register-to-register architecture allows each register to function as an accumulator, improving execution time and d ecreasing the required program memory ? software stack allows much greater dept h in subroutine calls and interrupts than hardware stacks ? compatible with existing z8 ? code ? expanded internal register file allows access of up to 4kb ? new instructions improve execution efficiency for code developed using higher-level programming languages, including c ? pipelined instruction fetch and execution ? new instructions for improv ed performance including bit, bswap, btj, cpc, ldc, ldci, lea, mult, and srl ? new instructions support 12-bit linea r addressing of the register file ? up to 10 mips operation ? c-compiler friendly ? 2-9 clock cycles per instruction for more information regardin g the ez8 cpu, refer to the ez8 cpu user manual avail- able for download at www.zilog.com . general purpose i/o the z8f082x, z8f081x, z8f042x, and z8f041x feature 11 to 19 port pins (ports a-c) for general purpose i/o (gpio). the number of gpio pins available is a function of package. each pin is individually programmable. flash controller the flash controller programs and erases the flash memory. 10-bit analog-to-digital converter the optional analog-to-digital converter (adc) converts an analog in put signal to a 10- bit binary number. the adc accepts inputs fr om 2 to 5 different analog input sources.
ps019707-1003 p r e l i m i n a r y introduction z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 5 uart the uart is full-duplex and capable of handling asynchronous data transfers. the uart supports 8- and 9-bit data modes and selectable parity. i 2 c the inter-integrated circuit (i 2 c ? ) controller makes the z8 encore! ? compatible with the i 2 c protocol. the i 2 c controller consists of two bidirec tional bus lines, a serial data (sda) line and a serial cl ock (scl) line. serial peripheral interface the serial peripheral interface (spi) allows the z8 encore! ? to exchange data between other peripheral devices such as eeproms, a/ d converters and isdn devices. the spi is a full-duplex, synchronous, character-oriented ch annel that supports a four-wire interface. timers two 16-bit reloadable timers can be used for timing/counting events or for motor control operations. these timers provide a 16-bit prog rammable reload counter and operate in one-shot, continuous, gated, capture, compare, capture and compare, and pwm modes. interrupt controller the z8f082x/z8f081x/z8f042x/z8f041x products support up to 18 interrupts. these interrupts consist of 7 internal peripheral in terrupts and 11 general- purpose i/o pin inter- rupt sources. the interrupts have 3 levels of programmable interrupt priority. reset controller the z8f082x family products can be reset using the reset pin, power-on reset, watch- dog timer (wdt), stop mode exit, or voltage brown-out (vbo) warning signal. on-chip debugger the z8f082x family products feature an in tegrated on-chip debugger (ocd). the ocd provides a rich set of debugging capabilities, such as reading and writing registers, pro- gramming the flash, setting breakpoints and executing code. a single-pin interface pro- vides communication to the ocd.
z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? ps019707-1003 p r e l i m i n a r y signal and pin descriptions 6 signal and pin descriptions overview the z8f082x family products ar e available in a variety of p ackages styles and pin config- urations. this chapter describes the signals an d available pin configur ations for each of the package styles. for informatio n regarding the physical pack age specifications, please refer to the chapter packaging on page 212. available packages table 2 identifies the package styles that ar e available for each device within the z8f082x family product line. pin configurations figures 2 through 5 illustrate the pin configura tions for all of the packages available in the z8f082x/z8f081x/z8f042x/z8f041x mcu family. refer to table 4 for a description of the signals. the analog input alternate functions (ana x ) are not available on the z8f081x and z8f041x devices. table 2. z8f082x family package options part number 10-bit adc 20-pin ssop and pdip 28-pin soic and pdip z8f0822 yes x z8f0821 yes x z8f0812 no x Z8F0811 no x z8f0422 yes x z8f0421 yes x z8f0412 no x z8f0411 no x note:
ps019707-1003 p r e l i m i n a r y signal and pin descriptions z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 7 figure 2. z8f0821 and z8f0421 in 20-pin ssop and pdip packages figure 3. z8f0822 and z8f0422 in 28-pin soic and pdip packages pc0 / t1in pb0 / ana0 pb1 / ana1 vref avss avdd dbg pa5 / txd0 pa4 / rxd0 pa6 / scl pa7 / sda reset vss xin xout vdd pa0 / t0in 1 pa3 / cts0 pa1 / t0out 5 10 pa2 / de0 2 3 4 6 7 8 9 20 16 11 19 18 17 15 14 13 12 pb0 / ana0 pb1 / ana1 pb2 / ana2 pb3 / ana3 pb4 / ana4 vref avss avdd dbg pc0 / t1in pa6 / scl pa7 / sda reset vss xin xout vdd 1 pc1 / t1out pc5 / miso 5 10 pc4 / mosi pc3 / sck pc2 / ss pa0 / t0in 14 pa1 / t0out 2 3 4 6 7 8 9 11 12 13 pa5 / txd0 pa4 / rxd0 pa3 / cts0 pa2 / de0 28 24 19 15 27 26 25 23 22 21 20 18 17 16
ps019707-1003 p r e l i m i n a r y signal and pin descriptions z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 8 figure 4. Z8F0811 and z8f0411 in 20-pin ssop and pdip packages figure 5. z8f0812 and z8f0412 in 28-pin soic and pdip packages pc0 / t1in pb0 pb1 no connect avss avdd dbg pa5 / txd0 pa4 / rxd0 pa6 / scl pa7 / sda reset vss xin xout vdd pa0 / t0in 1 pa3 / cts0 pa1 / t0out 5 10 pa2 / de0 2 3 4 6 7 8 9 20 16 11 19 18 17 15 14 13 12 pb0 pb1 pb2 pb3 pb4 no connect avss avdd dbg pc0 / t1in pa6 / scl pa7 / sda reset vss xin xout vdd 1 pc1 / t1out pc5 / miso 5 10 pc4 / mosi pc3 / sck pc2 / ss pa0 / t0in 14 pa1 / t0out 2 3 4 6 7 8 9 11 12 13 pa5 / txd0 pa4 / rxd0 pa3 / cts0 pa2 / de0 28 24 19 15 27 26 25 23 22 21 20 18 17 16
ps019707-1003 p r e l i m i n a r y signal and pin descriptions z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 9 signal descriptions table 3 describes the z8f082x family signals. refer to the section pin configurations on page 6 to determine the signals availabl e for the specific package styles. table 3. signal descriptions signal mnemonic i/o description general-purpose i/o ports a-h pa[7:0] i/o port c. these pins are used for general-purpose i/o. pb[4:0] i/o port b. these pins are used for general-purpose i/o. pc[5:0] i/o port c. these pins are used for general-purpose i/o. i 2 c controller scl i/o serial clock. this open-drain pin cl ocks data transfers in accordance with the i 2 c standard protocol. this pin is multiplexed with a general-purpose i/o pin. when the general-purpose i/o pin is configured for alternate function to enable the scl function, this pin is open-drain. sda i/o serial data. this open-drain pin transfers data between the i 2 c and a slave. this pin is multiplexed with a general-purpose i/o pin. when the general-purpose i/o pin is configured for alternate function to enable the sda function, this pin is open-drain. spi controller ss i/o slave select. this signal can be an output or an input. if the z8 encore! ? is the spi master, this pin may be configured as the slave select output. if the z8 encore! tm is the spi slave, this pin is the input slave select. it is multiplexed with a general-purpose i/o pin. sck i/o spi serial clock. the spi master supplies this pin. if the z8 encore! ? is the spi master, this pin is an output. if the z8 encore! ? is the spi slave, this pin is an input. it is multiplexed with a general-purpose i/o pin. mosi i/o master out slave in. this signal is th e data output from the spi master device and the data input to the spi slave device. it is multiplexed with a general-purpose i/o pin. miso i/o master in slave out. this pin is the data input to the spi master device and the data output from the spi slave device. it is multiplexed with a general-purpose i/o pin. uart controllers txd0 o transmit data. this signal is the tr ansmit outputs from the uart and irda. the txd signals are multiplexed with general-purpose i/o pins. rxd0 i receive data. this signal is the recei ver inputs for the uart and irda. the rxd signals are multiplexed with general-purpose i/o pins.
ps019707-1003 p r e l i m i n a r y signal and pin descriptions z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 10 cts0 i clear to send. this signal is control inputs for the uart. the cts signals are multiplexed with general-purpose i/o pins. de0 o driver enable. this signal allows automati c control of external rs-485 drivers. this signal is approximately the inverse of the txe (transmit empty) bit in the uart status 0 register. the de signal may be used to ensure the external rs-485 driver is enabled when data is transmitted by the uart. timers t0out / t1out o timer output 0-1. these signals are output pins from the timers. the timer output signals are multiplexed with general-purpose i/o pins. t0in / t1in i timer input 0-1. these signals are us ed as the capture, gating and counter inputs. the timer input signals are multiplexed with general-purpose i/o pins. analog ana[4:0] i analog input. these signals are inputs to the analog-to-digital converter (adc). the adc analog inputs are multiplexed with general-purpose i/o pins. vref i analog-to-digital converter reference voltage input. as an output, the vref signal is not recommended for use as a reference voltage for external devices. if the adc is configured to use the internal reference voltage generator, this pin should be left unconnected or capacitively coupled to analog ground (avss). oscillators xin i external crystal input. this is the input pin to the crystal oscillator. a crystal can be connected between it and the xout pin to form the oscillator. in addition, this pin is used with external rc networks or external clock drivers to provide the system clock to the system. xout o external crystal output. this pin is the output of the crystal oscillator. a crystal can be connected between it and the xin pin to form the oscillator. when the system clock is referred to in this manual, it refers to the freque ncy of the signal at this pin. this pin must be left unconnected when not using a crystal. on-chip debugger dbg i/o debug. this pin is the control and data input and output to and from the on-chip debugger. this pin is open-drain. for operation of the on-chip debugger, all power pins (v dd and av dd ) must be supplied with power and all ground pins (v ss and av ss ) must be properly grounded. the dbg pin is open-drain and must have an external pull-up resistor to ensure proper operation. table 3. signal descriptions (continued) signal mnemonic i/o description caution:
ps019707-1003 p r e l i m i n a r y signal and pin descriptions z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 11 pin characteristics table 4 provides detailed info rmation on the characteristics for each pin available on the z8f082x family products. data in table 4 is sorted alphabetically by the pin symbol mne- monic. reset reset i reset. generates a reset when asserted (driven low). power supply vdd i digital power supply. avdd i analog power supply. must be powered up and grounded to vdd, even if not using analog features. vss i digital ground. avss i analog ground. must be grounded and connected to vss, even if not using analog features. table 4. pin characteristics symbol mnemonic direction reset direction active low or active high tri-state output internal pull-up or pull-down schmitt trigger input open drain output avdd n/a n/a n/a n/a no no n/a avss n/a n/a n/a n/a no no n/a dbg i/o i n/a yes no yes yes pa[7:0] i/o i n/a yes programmable pull-up yes yes, programmable pb[4:0] i/o i n/a yes programmable pull-up yes yes, programmable pc[5:0] i/o i n/a yes programmable pull-up yes yes, programmable reset iilown/apull-upyesn/a vdd n/a n/a n/a n/a no no n/a vref analog n/a n/a n/a no no n/a table 3. signal descriptions (continued) signal mnemonic i/o description
ps019707-1003 p r e l i m i n a r y signal and pin descriptions z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 12 vss n/a n/a n/a n/a no no n/a xin i i n/a n/a no no n/a xout o o n/a no no no no table 4. pin charact eristics (continued) symbol mnemonic direction reset direction active low or active high tri-state output internal pull-up or pull-down schmitt trigger input open drain output
z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? ps019707-1003 p r e l i m i n a r y address space 13 address space overview the ez8 cpu can access three distinct address spaces: ? the register file contains addresses for the general-purpose registers and the ez8 cpu, peripheral, and general-purp ose i/o port control registers. ? the program memory contains addresses for all memory locations having executable code and/or data. ? the data memory contains addresses for all memory locations that hold data only. these three address spaces are covered brie fly in the following subsections. for more detailed information regarding the ez8 cp u and its address space, refer to the ez8 cpu user manual available for download at www.zilog.com . register file the register file address space in the z8 encore! ? is 4kb (4096 bytes). the register file is composed of two sections?control regist ers and general-purpose registers. when instructions are execut ed, registers are read from when defined as sources and written to when defined as destinations. the architecture of the ez8 cpu allows all general-purpose registers to function as accumulators, address pointers, index registers, stack areas, or scratch pad memory. the upper 256 bytes of the 4kb register file address space are reserved for control of the ez8 cpu, the on-chip peripherals, and the i/o ports. these registers are located at addresses from f00h to fffh . some of the addresses within the 256-byte control register section are reserved (unavailable). reading from an reserved register file addresses returns an undefined value. writing to re served register file addresses is not recom- mended and can produce unpredictable results. the on-chip ram always begins at address 00 0h in the register file address space. the z8f082x, z8f081x, z8f042x, and z8f041x contain 1kb of on-chip ram. reading from register file addresses outside the availabl e ram addresses (and not within the control register address space) returns an undefined va lue. writing to these register file addresses produces no effect.
ps019707-1003 p r e l i m i n a r y address space z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 14 program memory the ez8 cpu supports 64kb of program memory address space. the z8f082x, z8f081x, z8f042x, and z8f041x contain 4kb to 8kb of on-chip flash memory in the program memory address space, dependin g upon the device. reading from program memory addresses outside the availa ble flash memory addresses returns ffh . writing to these unimplemented program memory addre sses produces no effect. table 5 describes the program memory maps for the z8f082x family products. data memory the z8f082x family does not use the ez8 cpu?s 64kb data memory address space. flash information area table 6 describes the z8f082x family flash in formation area. this 512 byte information area is accessed by setting bit 7 of the flash page select register to 1. when access is enabled, the flash information area is mapped into the program memory and overlays the 512 bytes at addresses fe00h to ffffh. when the information area access is enabled, table 5. z8f082x family program memory maps program memory address (hex) function z8f082x and z8f081x products 0000-0001 option bits 0002-0003 reset vector 0004-0005 wdt interrupt vector 0006-0007 illegal instruction trap 0008-0037 interrupt vectors* 0038-1fff program memory z8f042x and z8f041x products 0000-0001 option bits 0002-0003 reset vector 0004-0005 wdt interrupt vector 0006-0007 illegal instruction trap 0008-0037 interrupt vectors* 0038-0fff program memory * see table 23 on page 49 for a list of the interrupt vectors.
ps019707-1003 p r e l i m i n a r y address space z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 15 all reads from these program memory addresses return the information area data rather than the program memory data . acces to the flash info rmation area is read-only. table 6. z8f082x family information area map program memory address (hex) function fe00h-fe3fh reserved fe40h-fe53h part number 20-character ascii alphanumeric code left justified and filled with zeros fe54h-ffffh reserved
z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? ps019707-1003 p r e l i m i n a r y register file address map 16 register file address map table 7 provides the address map for the register file of the z8f082x family of products. not all devices and package styles in the z8f0 82x family support the adc, the spi, or all of the gpio ports. consider registers for unimplemented peripherals as reserved. table 7. register file address map address (hex) register description mnemonic reset (hex) page # general purpose ram 000-3ff general-purpose register file ram ? xx 400-eff reserved ? xx timer 0 f00 timer 0 high byte t0h 00 69 f01 timer 0 low byte t0l 01 69 f02 timer 0 reload high byte t0rh ff 70 f03 timer 0 reload low byte t0rl ff 70 f04 timer 0 pwm high byte t0pwmh 00 72 f05 timer 0 pwm low byte t0pwml 00 72 f06 timer 0 control 0 t0ctl0 00 73 f07 timer 0 control 1 t0ctl1 00 73 timer 1 f08 timer 1 high byte t1h 00 69 f09 timer 1 low byte t1l 01 69 f0a timer 1 reload high byte t1rh ff 70 f0b timer 1 reload low byte t1rl ff 70 f0c timer 1 pwm high byte t1pwmh 00 72 f0d timer 1 pwm low byte t1pwml 00 72 f0e timer 1 control 0 t1ctl0 00 73 f0f timer 1 control 1 t1ctl1 00 73 f10-f3f reserved ? xx uart 0 f40 uart0 transmit data u0txd xx 92 uart0 receive data u0rxd xx 93 f41 uart0 status 0 u0stat0 0000011xb 93 f42 uart0 control 0 u0ctl0 00 95 f43 uart0 control 1 u0ctl1 00 95 f44 uart0 status 1 u0stat1 00 93 xx=undefined
ps019707-1003 p r e l i m i n a r y register file address map z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 17 f45 uart0 address compare register u0addr 00 98 f46 uart0 baud rate high byte u0brh ff 99 f47 uart0 baud rate low byte u0brl ff 99 f48-f4f reserved ? xx i 2 c f50 i 2 c data i2cdata 00 127 f51 i 2 c status i2cstat 80 128 f52 i 2 c control i2cctl 00 129 f53 i 2 c baud rate high byte i2cbrh ff 130 f54 i 2 c baud rate low byte i2cbrl ff 130 f55 i 2 c diagnostic state i2cdst xx000000b 132 f56 i 2 c diagnostic control i2cdiag 00 132 f57-f5f reserved ? xx serial peripheral interface (spi) un available in 20-pin package devices f60 spi data spidata 01 114 f61 spi control spictl 00 115 f62 spi status spistat 00 116 f63 spi mode spimode 00 118 f64 spi diagnostic state spidst 00 119 f65 reserved ? xx f66 spi baud rate high byte spibrh ff 120 f67 spi baud rate low byte spibrl ff 120 f68-f6f reserved ? xx analog-to-digital converter (adc) f70 adc control adcctl 20 136 f71 reserved ? xx f72 adc data high byte adcdh xx 137 f73 adc data low bits adcdl xx 138 f74-fbf reserved ? xx interrupt controller fc0 interrupt request 0 irq0 00 52 fc1 irq0 enable high bit irq0enh 00 55 fc2 irq0 enable low bit irq0enl 00 55 fc3 interrupt request 1 irq1 00 53 fc4 irq1 enable high bit irq1enh 00 56 fc5 irq1 enable low bit irq1enl 00 56 fc6 interrupt request 2 irq2 00 54 fc7 irq2 enable high bit irq2enh 00 57 fc8 irq2 enable low bit irq2enl 00 57 fc9-fcc reserved ? xx table 7. register file address map (continued) address (hex) register description mnemonic reset (hex) page # xx=undefined
ps019707-1003 p r e l i m i n a r y register file address map z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 18 fcd interrupt edge select irqes 00 58 fce reserved ? 00 fcf interrupt control irqctl 00 59 gpio port a fd0 port a address paaddr 00 40 fd1 port a control pactl 00 41 fd2 port a input data pain xx 46 fd3 port a output data paout 00 47 gpio port b fd4 port b address pbaddr 00 40 fd5 port b control pbctl 00 41 fd6 port b input data pbin xx 46 fd7 port b output data pbout 00 47 gpio port c fd8 port c address pcaddr 00 40 fd9 port c control pcctl 00 41 fda port c input data pcin xx 46 fdb port c output data pcout 00 47 fdc-fef reserved ? xx watch-dog timer (wdt) ff0 watch-dog timer control wdtctl xxx00000b 78 ff1 watch-dog timer reload upper byte wdtu ff 80 ff2 watch-dog timer relo ad high byte wdth ff 80 ff3 watch-dog timer relo ad low byte wdtl ff 80 ff4-ff7 reserved ? xx flash memory controller ff8 flash control fctl 00 145 ff8 flash status fstat 00 146 ff9 flash page select fps 00 147 ff9 (if enabled) flash sector protect fprot 00 148 ffa flash programming frequency high byte ffreqh 00 149 ffb flash programming frequency low byte ffreql 00 149 read-only memory ez8 cpu ffc flags ? xx refer to the ez8 cpu user manual ffd register pointer rp xx ffe stack pointer high byte sph xx fff stack pointer low byte spl xx table 7. register file address map (continued) address (hex) register description mnemonic reset (hex) page # xx=undefined
ps019707-1003 p r e l i m i n a r y contol register summary z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 19 contol register summary timer 0 high byte t0h (%f00 - read/write) d7 d6 d5 d4 d3 d2 d1 d0 timer 0 current count value [15:8] timer 0 low byte t0l (%f01 - read/write) d7 d6 d5 d4 d3 d2 d1 d0 timer 0 current count value [7:0] timer 0 reload high byte t0rh (%f02 - read/write) d7 d6 d5 d4 d3 d2 d1 d0 timer 0 reload value [15:8] timer 0 reload low byte t0rl (%f03 - read/write) d7 d6 d5 d4 d3 d2 d1 d0 timer 0 reload value [7:0] timer 0 pwm high byte t0pwmh (%f04 - read/write) d7 d6 d5 d4 d3 d2 d1 d0 timer 0 pwm value [15:8] timer 0 control 0 t0ctl0 (%f06 - read/write) d7 d6 d5 d4 d3 d2 d1 d0 reserved cascade timer 0 = timer 0 input signal is gpio pin 1 = timer 0 input signal is timer 1 out reserved timer 0 control 1 t0ctl1 (%f07 - read/write) d7 d6 d5 d4 d3 d2 d1 d0 timer mode 000 = one-shot mode 001 = continuous mode 010 = counter mode 011 = pwm mode 100 = capture mode 101 = compare mode 110 = gated mode 111 = capture/compare mode prescale value 000 = divide by 1 001 = divide by 2 010 = divide by 4 011 = divide by 8 100 = divide by 16 101 = divide by 32 110 = divide by 64 111 = divide by 128 timer input/output polarity operation of this bit is a function of the current opera ting mode of the timer timer enable 0 = timer is disabled 1 = timer is enabled timer 1 high byte t1h (%f08 - read/write) d7 d6 d5 d4 d3 d2 d1 d0 timer 1 current count value [15:8] timer 1 low byte t1l (%f09 - read/write) d7 d6 d5 d4 d3 d2 d1 d0 timer 1 current count value [7:0] timer 1 reload high byte t1rh (%f0a - read/write) d7 d6 d5 d4 d3 d2 d1 d0 timer 1 reload value [15:8] timer 1 reload low byte t1rl (%f0b - read/write) d7 d6 d5 d4 d3 d2 d1 d0 timer 1 reload value [7:0]
ps019707-1003 p r e l i m i n a r y contol register summary z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 20 timer 1 pwm high byte t1pwmh (%f0c - read/write) d7 d6 d5 d4 d3 d2 d1 d0 timer 1 pwm value [15:8] timer 1 pwm low byte t1pwml (%f0d - read/write) d7 d6 d5 d4 d3 d2 d1 d0 timer 1 pwm value [7:0] timer 1 control 0 t1ctl0 (%f0e - read/write) d7 d6 d5 d4 d3 d2 d1 d0 reserved cascade timer 0 = timer 1 input signal is gpio pin 1 = timer 1 input signal is timer 0 out reserved timer 1 control 1 t1ctl1 (%f0f - read/write) d7 d6 d5 d4 d3 d2 d1 d0 timer mode 000 = one-shot mode 001 = continuous mode 010 = counter mode 011 = pwm mode 100 = capture mode 101 = compare mode 110 = gated mode 111 = capture/compare mode prescale value 000 = divide by 1 001 = divide by 2 010 = divide by 4 011 = divide by 8 100 = divide by 16 101 = divide by 32 110 = divide by 64 111 = divide by 128 timer input/output polarity operation of this bit is a function of the current opera ting mode of the timer timer enable 0 = timer is disabled 1 = timer is enabled uart0 transmit data u0txd (%f40 - write only) d7 d6 d5 d4 d3 d2 d1 d0 uart0 transmitter data byte [7:0] uart0 receive data u0rxd (%f40 - read only) d7 d6 d5 d4 d3 d2 d1 d0 uart0 receiver data byte [7:0] uart0 status 0 u0stat0 (%f41 - read only) d7 d6 d5 d4 d3 d2 d1 d0 cts signal returns the level of the cts signal transmitter empty 0 = data is currently transmitting 1 = transmission is complete transmitter data register empty 0 = transmit data register is full 1 = transmit data register is empty break detect 0 = no break occurred 1 = a break occurred framing error 0 = no framing error occurred 1 = a framing occurred overrun error 0 = no overrrun error occurred 1 = an overrun error occurred parity error 0 = no parity error occurred 1 = a parity error occurred receive data available 0 = receive data register is empty 1 = a byte is available in the receive data register
ps019707-1003 p r e l i m i n a r y contol register summary z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 21 uart0 control 0 u0ctl0 (%f42 - read/write) d7 d6 d5 d4 d3 d2 d1 d0 loop back enable 0 = normal operation 1 = transmit data is looped back to the receiver stop bit select 0 = transmitter sends 1 stop bit 1 = transmitter sends 2 stop bits send break 0 = no break is sent 1 = output of the transmitter is zero parity select 0 = even parity 1 = odd parity parity enable 0 = parity is disabled 1 = parity is enabled cts enable 0 = cts signal has no effect on the transmitter 1 = uart recognizes cts signal as a transmit enable control signal receive enable 0 = receiver disabled 1 = receiver enabled transmit enable 0 = transmitter disabled 1 = transmitter enabled uart0 control 1 u0ctl1 (%f43 - read/write) d7 d6 d5 d4 d3 d2 d1 d0 infrared encoder/decoder enable 0 = infrared endec is disabled 1 = infrared endec is enabled received data interrupt enable 0 = received data and errors generate interrupt requests 1 = only errors generate interrupt requests. received data does not. baud rate registers control refer to uart chapter for operation driver enable polarity 0 = de signal is active high 1 = de signal is active low multiprocessor bit transmit 0 = send a 0 as the multiprocessor bit 1 = send a 1 as the multiprocessor bit multiprocessor mode [0] see multiprocessor mode [1] below multiprocessor (9 -bit) enable 0 = multiprocessor mode is disabled 1 = multiprocessor mode is enabled multiprocessor mode [1] with multiprocess mode bit 0: 00 = interrupt on all received bytes 01 = interrupt only on address bytes 10 = interrupt on address match and following data 11 = interrupt on data following an address match uart0 status 1 u0stat1 (%f44- read only) d7 d6 d5 d4 d3 d2 d1 d0 mulitprocessor receive returns value of la st multiprocessor bit new frame 0 = current byte is not start of frame 1 = current byte is start of new frame reserved uart0 address compare u0addr (%f45 - read/write) d7 d6 d5 d4 d3 d2 d1 d0 uart0 address compare [7:0]
ps019707-1003 p r e l i m i n a r y contol register summary z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 22 uart0 baud rate generator high byte u0brh (%f46 - read/write) d7 d6 d5 d4 d3 d2 d1 d0 uart0 baud rate divisor [15:8] uart0 baud rate generator low byte u0brl (%f47 - read/write) d7 d6 d5 d4 d3 d2 d1 d0 uart0 baud rate divisor [7:0] i2c data i2cdata (%f50 - read/write) d7 d6 d5 d4 d3 d2 d1 d0 i2c data [7:0] i2c status i2cstat (%f51 - read only) d7 d6 d5 d4 d3 d2 d1 d0 nack interrupt 0 = no action required to service nak 1 = start/stop not set after nak data shift state 0 = data is not being transferred 1 = data is being transferred transmit address state 0 = address is not being transferred 1 = address is being transferred read 0 = write operation 1 = read operation 10-bit address 0 = 7-bit address being transmitted 1 = 10-bit addres s being transmitted acknowledge 0 = acknowledge not transmitted/received 1 = for last byte, acknowledge was transmitted/received receive data register full 0 = i2c has not received data 1 = data register contains received data transmit data register empty 0 = data register is full 1 = data register is empty i2c control i2cctl (%f52 - read/write) d7 d6 d5 d4 d3 d2 d1 d0 i2c signal filter enable 0 = digital filtering disabled 1 = low-pass digital filters enabled on sda and scl input signals flush data 0 = no effect 1 = clears i2c data register send nak 0 = do not send nak 1 = send nak after next byte received from slave enable tdre interrupts 0 = do not generate an interrupt when the i2c data register is empty 1 = generate an interrupt when the i2c transmit data register is empty baud rate generator interrupt request 0 = interrupts behave as set by i2c control 1 = brg generates an interrupt when it counts down to zero send stop condition 0 = do not issue stop condition after data transmission is complete 1 = issue stop condition after data transmission is complete send start condition 0 = do not send start condition 1 = send start condition i2c enable 0 = i2c is disabled 1 = i2c is enabled i2c baud rate generator high byte i2cbrh (%f53 - read/write) d7 d6 d5 d4 d3 d2 d1 d0 i2c baud rate divisor [15:8] i2c baud rate generator low byte i2cbrl (%f54 - read/write) d7 d6 d5 d4 d3 d2 d1 d0 i2c baud rate divisor [7:0]
ps019707-1003 p r e l i m i n a r y contol register summary z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 23 spi data spidata (%f60 - read/write) d7 d6 d5 d4 d3 d2 d1 d0 spi data [7:0] spi control spictl (%f61 - read/write) d7 d6 d5 d4 d3 d2 d1 d0 spi enable 0 = spi disabled 1 = spi enabled master mode enabled 0 = spi configured in slave mode 1 = spi configured in master mode wire-or (open-drain) mode enabled 0 = spi signals not configured for open-drain 1 = spi signals (sck, ss , miso, and mosi) configured for open-drain clock polarity 0 = sck idles low 1 = spi idles high phase select sets the phase relationship of the data to the clock. brg timer interrupt request 0 = brg timer function is disabled 1 = brg time-out in terrupt is enabled start an spi interrupt request 0 = no effect 1 = generate an spi interrupt request interrupt request enable 0 = spi interrupt requests are disabled 1 = spi interrupt requests are enabled spi status spistat (%f62 - read only) d7 d6 d5 d4 d3 d2 d1 d0 slave select 0 = if slave, ss pin is asserted 1 = if slave, ss pin is not asserted transmit status 0 = no data transmission in progress 1 = data transmission now in progress reserved slave mode transaction abort 0 = no slave mode transaction abort detected 1 = slave mode transaction abort was detected collision 0 = no multi-master collision detected 1 = multi-master collision was detected overrun 0 = no overrun error detected 1 = overrun error was detected interrupt request 0 = no spi inte rrupt request pending 1 = spi interrup t request is pending spi mode spimode (%f63 - read/write) d7 d6 d5 d4 d3 d2 d1 d0 slave select value if master and spimode[1] = 1: 0 = ss pin driven low 1 = ss pin driven high slave select i/o 0 = ss pin configured as an input 1 = ss pin configured as an output (master mode only) number of data bits per character 000 = 8 bits 001 = 1 bit 010 = 2 bits 011 = 3 bits 100 = 4 bits 101 = 5 bit 110 = 6 bits 111 = 7 bits diagnostic mode control 0 = reading from spibrh, spibrl returns reload values 1 = reading from spibrh, spibrl returns current brg count value reserved
ps019707-1003 p r e l i m i n a r y contol register summary z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 24 spi diagnostic state spidst (%f64 - read only) d7 d6 d5 d4 d3 d2 d1 d0 spi state transmit clock enable 0 = internal transmit clock enable signal is deasserted 1 = internal transmit clock enable signal is asserted shift clock enable 0 = internal shift clock enable signal is deasserted 1 = internal shift clock enable signal is asserted spi baud rate generator high byte spibrh (%f66 - read/write) d7 d6 d5 d4 d3 d2 d1 d0 spi baud rate divisor [15:8] spi baud rate generator low byte spibrl (%f67 - read/write) d7 d6 d5 d4 d3 d2 d1 d0 spi baud rate divisor [7:0] adc control adcctl (%f70 - read/write) d7 d6 d5 d4 d3 d2 d1 d0 analog input select 0000 = ana0 0001 = ana1 0010 = ana2 0011 = ana3 0100 = ana4 0101 through 21111 = reserved continuous mode select 0 = single-shot conversion 1 = continuous conversion external vref select 0 = internal voltage reference selected 1 = external voltage reference selected reserved conversion enable 0 = conversion is complete 1 = begin conversion adc data high byte adcd_h (%f72 - read only) d7 d6 d5 d4 d3 d2 d1 d0 adc data [9:2] adc data low bits adcd_l (%f73 - read only) d7 d6 d5 d4 d3 d2 d1 d0 reserved adc data [1:0] interrupt request 0 irq0 (%fc0 - read/write) d7 d6 d5 d4 d3 d2 d1 d0 adc interrupt request spi interrupt request i2c interrupt request uart 0 transmitter interrupt request uart 0 receiver interrupt request timer 0 interrupt request timer 1 interrupt request reserved for all of the above peripherals: 0 = peripheral irq is not pending 1 = peripheral irq is awaiting service irq0 enable high bit irq0enh (%fc1 - read/write) d7 d6 d5 d4 d3 d2 d1 d0 adc irq enable hit bit spi irq enable high bit i2c irq enable high bit uart 0 transmitter irq enable high uart 0 receiver irq enable high bit timer 0 irq enable high bit timer 1 irq enable high bit reserved
ps019707-1003 p r e l i m i n a r y contol register summary z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 25 irq0 enable low bit irq0enl (%fc2 - read/write) d7 d6 d5 d4 d3 d2 d1 d0 adc irq enable hit bit spi irq enable low bit i2c irq enable low bit uart 0 transmitter irq enable low uart 0 receiver irq enable low bit timer 0 irq enable low bit timer 1 irq enable low bit reserved interrupt request 1 irq1 (%fc3 - read/write) d7 d6 d5 d4 d3 d2 d1 d0 port a pin interrupt request 0 = irq from corresponding pin [7:0] is not pending 1 = irq from corresponding pin [7:0] is awaiting service irq1 enable high bit irq1enh (%fc4 - read/write) d7 d6 d5 d4 d3 d2 d1 d0 port a pin irq enable high bit irq1 enable low bit irq1enl (%fc5 - read/write) d7 d6 d5 d4 d3 d2 d1 d0 port a pin irq enable low bit interrupt request 2 irq2 (%fc6 - read/write) d7 d6 d5 d4 d3 d2 d1 d0 port c pin interrupt request 0 = irq from corresponding pin [3:0] is not pending 1 = irq from corresponding pin [3:0] is awaiting service reserved irq2 enable high bit irq2enh (%fc7 - read/write) d7 d6 d5 d4 d3 d2 d1 d0 port c pin irq enable high bit reserved irq2 enable low bit irq2enh (%fc8 - read/write) d7 d6 d5 d4 d3 d2 d1 d0 port c pin irq enable low bit reserved interrupt control irqes (%fcd - read/write) d7 d6 d5 d4 d3 d2 d1 d0 reserved interrupt request enable 0 = interrupts are disabled 1 = interrupts are enabled port a address paaddr (%fd0 - read/write) d7 d6 d5 d4 d3 d2 d1 d0 port a address[7:0] selects port sub-registers: 00h = no function 01h = data direction 02h = alternate function 03h = output control (open-drain) 04h = high drive enable 05h = stop mode recovery enable 06h = pull-up enable 07h-ffh = no function port a control pactl (%fd1 - read/write) d7 d6 d5 d4 d3 d2 d1 d0 port a control[7:0] provides access to port sub-registers
ps019707-1003 p r e l i m i n a r y contol register summary z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 26 port a input data pain (%fd2 - read only) d7 d6 d5 d4 d3 d2 d1 d0 port a input data [7:0] port a output data paout (%fd3 - read/write) d7 d6 d5 d4 d3 d2 d1 d0 port a output data [7:0] port b address pbaddr (%fd4 - read/write) d7 d6 d5 d4 d3 d2 d1 d0 port b address[7:0] selects port sub-registers: 00h = no function 01h = data direction 02h = alternate function 03h = output control (open-drain) 04h = high drive enable 05h = stop mode recovery enable 06h = pull-up enable 07h-ffh = no function port b control pbctl (%fd5 - read/write) d7 d6 d5 d4 d3 d2 d1 d0 port b control [4:0] provides access to port sub-registers reserved port b input data pbin (%fd6 - read only) d7 d6 d5 d4 d3 d2 d1 d0 port b input data [4:0] reserved port b output data pbout (%fd7 - read/write) d7 d6 d5 d4 d3 d2 d1 d0 port b output data [4:0] reserved port c address pcaddr (%fd8 - read/write) d7 d6 d5 d4 d3 d2 d1 d0 port c address[7:0] selects port sub-registers: 00h = no function 01h = data direction 02h = alternate function 03h = output control (open-drain) 04h = high drive enable 05h = stop mode recovery enable 06h = pull-up enable 07h-ffh = no function port c control pcctl (%fd9 - read/write) d7 d6 d5 d4 d3 d2 d1 d0 port c control [5:0] provides access to port sub-registers reserved port c input data pcin (%fda - read only) d7 d6 d5 d4 d3 d2 d1 d0 port c input data [5:0] reserved port c output data pcout (%fdb - read/write) d7 d6 d5 d4 d3 d2 d1 d0 port c output data [5:0] reserved
ps019707-1003 p r e l i m i n a r y contol register summary z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 27 watch-dog timer control wdtctl (%ff0 - read only) d7 d6 d5 d4 d3 d2 d1 d0 reserved ext 0 = reset not generated by reset pin 1 = reset generated by reset pin wdt 0 = wdt timeout has not occurred 1 = wdt timeout occurred stop 0 = smr has not occurred 1 = smr has occurred por 0 = por has not occurred 1 = por has occurred watch-dog timer reload upper byte wdtu (%ff1 - read/write) d7 d6 d5 d4 d3 d2 d1 d0 wdt reload value [23:16] watch-dog timer reload middle byte wdth (%ff2 - read/write) d7 d6 d5 d4 d3 d2 d1 d0 wdt reload value [15:8] watch-dog timer reload low byte wdtl (%ff3 - read/write) d7 d6 d5 d4 d3 d2 d1 d0 wdt reload value [7:0] flash control fctl (%ff8 - write only) d7 d6 d5 d4 d3 d2 d1 d0 flash command 73h = first unlock command 8ch = second unlock command 95h = page erase command 63h = mass erase command 5eh = flash sector protect reg select flash status fstat (%ff8 - read only) d7 d6 d5 d4 d3 d2 d1 d0 flash controller status 00_0000 = flash controller locked 00_0001 = first unlock received 00_0010 = second unlock received 00_0011 = flash controller unlocked 00_0100 = flash sector protect register selected 00_1xxx = programming in progress 01_0xxx = page erase in progress 10_0xxx = mass erase in progress reserved flash page select fps (%ff9 - read/write) d7 d6 d5 d4 d3 d2 d1 d0 flash page select [6:0] identifies the flash memory page for page erase operation. information area enable flash sector protect fprot (%ff9 - read/write to 1?s) d7 d6 d5 d4 d3 d2 d1 d0 flash sector protect [7:0] 0 = sector can be programmed or erased from user code 1 = sector is protected and cannot be programmed or erased from user code flash frequency high byte ffreqh (%ffa - read/write) d7 d6 d5 d4 d3 d2 d1 d0 flash frequency value [15:8] flash frequency low byte ffreql (%ffb - read/write) d7 d6 d5 d4 d3 d2 d1 d0 flash frequency value [7:0]
ps019707-1003 p r e l i m i n a r y contol register summary z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 28 flags flags (%ffc - read/write) d7 d6 d5 d4 d3 d2 d1 d0 f1 - user flag 1 f2 - user flag 2 h - half carry d - decimal adjust v - overflow flag s - sign flag z - zero flag c - carry flag register pointer rp (%ffd - read/write) d7 d6 d5 d4 d3 d2 d1 d0 working register page address [11:8] working register group address [7:4] stack pointer high byte sph (%ffe - read/write) d7 d6 d5 d4 d3 d2 d1 d0 stack pointer [15:8] stack pointer low byte spl (%fff - read/write) d7 d6 d5 d4 d3 d2 d1 d0 stack pointer [7:0]
z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? ps019707-1003 p r e l i m i n a r y reset and stop mode recovery 29 reset and stop mode recovery overview the reset controller within the z8f082x fam ily controls reset and stop mode recov- ery operation. in typical operation, the following events cause a reset to occur: ? power-on reset (por) ? voltage brown-out (vbo) ? watch-dog timer time-out (when configured via the wdt_res option bit to initiate a reset) ? external reset pin assertion ? on-chip debugger initiated reset (ocdctl[0] set to 1) when the z8f082x family device is in stop mode, a stop mode recovery is initiated by either of the following: ? watch-dog timer time-out ? gpio port input pin transition on an enabled stop mode recovery source ? dbg pin driven low reset types the z8f082x family provides two different types of reset operation (system reset and stop mode recovery). the type of reset is a function of both the current operating mode of the z8f082x family device and the source of the reset. table 7 lists the types of reset and their operating characteristics. table 7. reset and stop mode reco very characteristics and latency reset type reset characteristics and latency control registers ez8 cpu reset latency (delay) system reset reset (as applicable) reset 66 wd t oscillator cycles + 16 system clock cycles stop mode recovery unaffected, except wdt_ctl register reset 66 wdt oscillator cycles + 16 system clock cycles
ps019707-1003 p r e l i m i n a r y reset and stop mode recovery z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 30 system reset during a system reset, the z8f082 x family device is held in reset for 66 cycles of the watch-dog timer oscillator followed by 16 cycl es of the system clock. at the beginning of reset, all gpio pins are configured as i nputs. all gpio programm able pull-ups are dis- abled. during reset, the ez8 cpu and on-chip peripher als are idle; however, the on-chip crystal oscillator and watch-dog timer os cillator continue to run. th e system clock begins oper- ating following the watch-dog timer oscillat or cycle count. the ez8 cpu and on-chip peripherals remain idle through th e 16 cycles of th e system clock. upon reset, control registers w ithin the register file that have a defined reset value are loaded with their reset values. other control registers (including the stack pointer, regis- ter pointer, and flags) and general-purpo se ram are undefined following reset. the ez8 cpu fetches the reset vector at program memory addresses 0002h and 0003h and loads that value into the program counter. prog ram execution begins at the reset vector address. reset sources table 8 lists the reset sources as a function of the operating mode. the text following pro- vides more detailed informatio n on the individual reset sour ces. please note that a power- on reset / voltage brown-out event always has priority over all other possible reset sources to insure a fu ll system reset occurs. power-on reset each device in the z8f082x family contains an internal power-on reset (por) circuit. the por circuit monitors the supply voltage an d holds the device in the reset state until table 8. reset sources and resulting reset type operating mode reset source reset type normal or halt modes power-on reset / voltage brown-out system reset watch-dog timer time-out when configured for reset system reset reset pin assertion system reset on-chip debugger initiated reset (ocdctl[0] set to 1) system reset except the on-chip debugger is unaffected by the reset stop mode power-on reset / voltage brown-out system reset reset pin assertion system reset dbg pin driven low system reset
ps019707-1003 p r e l i m i n a r y reset and stop mode recovery z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 31 the supply voltage reaches a safe operating le vel. after the supply voltage exceeds the por voltage threshold (v por ), the por counter is enabled and counts 66 cycles of the watch-dog timer oscillator. after the por counter times out, the xtal counter is enabled to count a total of 16 system clock pulses. the device is held in the reset state until both the por counter and xtal counter have timed out. after the z8f082x family device exits the power-on reset state, the ez8 cpu fetches the reset vector. following power-on reset, the por status bit in the watch-dog ti mer control (wdtctl) register is set to 1. figure 6 illustrates power-on r eset operation. refer to the electrical characteristics chapter for the por threshold voltage (v por ). figure 6. power-on reset operation) voltage brown-out reset the devices in the z8f082x family provid e low voltage brown-out (vbo) protection. the vbo circuit senses when the supply voltage drops to an unsafe level (below the vbo threshold voltage) and forces the device into the reset state. while the supply voltage remains below the power-on reset voltage threshold (v por ), the vbo block holds the device in the reset state. vcc = 0.0v vcc = 3.3v v por v vbo primary oscillator internal reset signal program execution oscillator start-up xtal wdt clock wdt osc counter delay counter delay not to scale
ps019707-1003 p r e l i m i n a r y reset and stop mode recovery z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 32 after the supply voltage again exceeds the po wer-on reset voltage threshold, the device progresses through a full system reset sequenc e, as described in the power-on reset sec- tion. following power-on reset, the por status bit in the watch-dog timer control (wdtctl) register is set to 1. figure 7 illust rates voltage brown-out operation. refer to the electrical characteristics chapter for the vbo and por threshold voltages (v vbo and v por ). the voltage brown-out circuit can be either enabled or disabled during stop mode. operation during stop mode is set by the vbo_ao option bit. refer to the option bits chapter for information on configuring vbo_ao . figure 7. voltage brown-out reset operation watch-dog timer reset if the device is in normal or halt mode, the watch-dog timer can initiate a system reset at time-out if the wdt_res option bit is set to 1. th is is the default (unpro- grammed) setting of the wdt_res option bit. the wdt status bit in the wdt control register is set to signify that the r eset was initiated by the watch-dog timer. v cc = 3.3v v por v vbo internal reset signal program execution program execution voltage brownout v cc = 3.3v primary oscillator wdt clock xtal wdt counter delay counter delay
ps019707-1003 p r e l i m i n a r y reset and stop mode recovery z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 33 external pin reset the reset pin has a schmitt-triggered input, an in ternal pull-up, and a digital filter to reject noise. once the reset pin is asserted for at least 4 system clock cycles, the device progresses through the system r eset sequence. while the reset input pin is asserted low, the z8f082x family device continues to be held in the reset state. if the reset pin is held low beyond the system reset time-ou t, the device exits the reset state immedi- ately following reset pin deassertion. following a syst em reset initiated by the exter- nal reset pin, the ext status bit in the watch-dog time r control (wdtctl) register is set to 1. stop mode recovery stop mode is entered by execution of a stop instruction by the ez8 cpu. refer to the low-power modes chapter for detailed stop mode information. during stop mode recovery, the device is held in reset for 66 cycles of the watch-dog timer oscillator fol- lowed by 16 cycles of the system clock. stop mode recovery only affects the contents of the watch-dog timer control register. stop mode recovery does not affect any other val- ues in the register file, including the stack po inter, register pointer, flags, peripheral control registers, and general-purpose ram. the ez8 cpu fetches the reset vector at program memory addresses 0002h and 0003h and loads that value into the program counte r. program execution begins at the reset vec- tor address. following stop mode recovery, the stop bit in the watch-dog timer con- trol register is set to 1. table 9 lists the stop mode recovery sources and resulting actions. the text following pr ovides more detailed informat ion on each of the stop mode recovery sources. stop mode recovery using watch-dog ti mer time-out if the watch-dog timer times out during stop mode, the device undergoes a stop mode recovery sequence. in the wa tch-dog timer control register, the wdt and stop bits are set to 1. if the watch- dog timer is configured to ge nerate an interrupt upon time- table 9. stop mode recovery sources and resulting action operating mode stop mode recovery source action stop mode watch-dog timer time-out when configured for reset stop mode recovery watch-dog timer time-out when configured for interrupt stop mode recovery followed by interrupt (if interrupts are enabled) data transition on any gpio port pin enabled as a stop mode recovery source stop mode recovery
ps019707-1003 p r e l i m i n a r y reset and stop mode recovery z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 34 out and the z8f082x family device is configured to respond to interrupts, the ez8 cpu services the watch-dog timer interrupt request following the normal stop mode recov- ery sequence. stop mode recovery using a gpio port pin transition each of the gpio port pins may be configured as a stop mode recovery input source. on any gpio pin enabled as a stop mode rec over source, a change in the input pin value (from high to low or from low to high) initiates stop mode recovery. the gpio stop mode recovery signals are filtered to reje ct pulses less than 10 ns (typical) in dura- tion. in the watch-dog timer control register, the stop bit is set to 1. in stop mode, the gpio po rt input data registers (p x in) are disabled. the port input data registers record the port transition only if the signal stays on the port pin through the end of the stop mode recovery delay. thus, short pulses on the port pin ca n initiate stop mode recovery with- out being written to the port input data register or without initiating an in- terrupt (if enabled for that pin). caution:
z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? ps019707-1003 p r e l i m i n a r y low-power modes 35 low-power modes overview the z8f082x family products contain power-saving features. the highest level of power reduction is provided by stop mode. the next level of power reduction is provided by the halt mode. stop mode execution of the ez8 cpu?s stop instructio n places the device into stop mode. in stop mode, the operating characteristics are: ? primary crystal oscillator is stopped; xin and xout pins are driven low. ? system clock is stopped ? ez8 cpu is stopped ? program counter (pc) stops incrementing ? if enabled for operation in stop mode, the watch-dog timer and its internal rc oscillator continue to operate ? if enabled for operation in stop mode via the associated option bit, the voltage- brown out protection circuit continues to operate ? all other on-chip peripherals are idle to minimize current in stop mode, the watch-dog timer should be disabled and all gpio pins that are configured as digital inputs must be driven to one of the supply rails (v cc or gnd). the device can be brought out of stop mode using stop mode recov- ery. for more information on stop mode re covery refer to the reset and stop mode recovery chapter on page 29. stop mode should not be used when driving the z8f082x family devices with an external clock driver sour ce (since the xin and xout pins are driven low in stop mode). caution:
ps019707-1003 p r e l i m i n a r y low-power modes z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 36 halt mode execution of the ez8 cpu?s halt instructio n places the device into halt mode. in halt mode, the operating characteristics are: ? primary crystal oscillator is en abled and continues to operate ? system clock is enabled and continues to operate ? ez8 cpu is stopped ? program counter (pc) stops incrementing ? watch-dog timer?s internal rc oscillator continues to operate ? if enabled, the watch-dog ti mer continues to operate ? all other on-chip peripherals continue to operate the ez8 cpu can be brought out of halt mode by any of the following operations: ? interrupt ? watch-dog timer time-out (interrupt or reset) ? power-on reset ? voltage-brown out reset ? external reset pin assertion to minimize current in halt mode, all gpio pi ns which are configured as inputs must be driven to one of the supply rails (v cc or gnd).
z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? ps019707-1003 p r e l i m i n a r y general-purpose i/o 37 general-purpose i/o overview the z8f082x family products support a maximum of 19 port pins (ports a-c) for gen- eral-purpose input/output (gpi/o) operations. each port contains control and data regis- ters. the gpio control registers are used to determine data direction, open-drain, output drive current, programmable pull-ups, stop mode recovery functionality, and alternate pin functions. each port pin is individually programmable. gpio port availability by device table 10 lists the port pins availabl e with each device and package type. architecture figure 8 illustrates a simplified block diagram of a gpio port pin. in this figure, the abil- ity to accommodate alternate fu nctions, variable port current drive strength, and program- mable pull-up are not illustrated. table 10. port availability by device and package type devices package port a port b port c z8f0821, Z8F0811, z8f0421, z8f0411 20 pin [7:0] [1:0] [0] z8f0822, z8f0812, z8f0422, z8f0412 28 pin [7:0] [4:0] [5:0]
ps019707-1003 p r e l i m i n a r y general-purpose i/o z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 38 figure 8. gpio port pin block diagram gpio alternate functions many of the gpio port pins can be used as bo th general-purpose i/o and to provide access to on-chip peripheral functions such as th e timers and serial communication devices. the port a-c alternate function sub-registers conf igure these pins for either general-purpose i/o or alternate function operation. when a pin is configured for alte rnate function, control of the port pin direction (input/output) is passed from the port a-c data direction regis- ters to the alternate function assi gned to this pin. table 11 lists the alternate functions asso- ciated with each port pin. d q dq d q gnd vdd port output control port data direction port output data register port input data register port pin data bus system clock system clock schmitt trigger
ps019707-1003 p r e l i m i n a r y general-purpose i/o z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 39 gpio interrupts many of the gpio port pins can be used as interrupt sources. some port pins may be con- figured to generate an interrupt request on eith er the rising edge or falling edge of the pin input signal. other port pin interrupts generate an interrupt when any edge occurs (both rising and falling). refer to the interrupt controller chapter for more information on interrupts using the gpio pins. table 11. port alternat e function mapping port pin mnemonic alternate function description port a pa0 t0in timer 0 input pa1 t0out timer 0 output pa2 de uart 0 driver enable pa3 cts0 uart 0 clear to send pa4 rxd0 / irrx0 uart 0 / irda 0 receive data pa5 txd0 / irtx0 uart 0 / irda 0 transmit data pa6 scl i 2 c clock (automatically open-drain) pa7 sda i 2 c data (automatically open-drain) port b pb0 ana0 adc analog input 0 pb1 ana1 adc analog input 1 pb2 ana2 adc analog input 2 pb3 ana3 adc analog input 3 pb4 ana4 adc analog input 4 port c pc0 t1in timer 1 input pc1 t1out timer 1 output pc2 ss spi slave select pc3 sck spi serial clock pc4 mosi spi master out slave in pc5 miso spi master in slave out
ps019707-1003 p r e l i m i n a r y general-purpose i/o z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 40 gpio control register definitions four registers for each port provide access to gpio control, input data, and output data. table 12 lists these port registers. use the po rt a-c address and control registers together to provide access to sub-registers fo r port configuration and control. port a-c address registers the port a-c address registers select the gp io port functionality accessible through the port a-c control registers. the port a-c ad dress and control registers combine to pro- vide access to all gpio port control (table 13). table 12. gpio port registers and sub-registers port register mnemonic port register name p x addr port a-c address register (selects sub-registers) p x ctl port a-c control register (provides access to sub-registers) p x in port a-c input data register p x out port a-c output data register port sub-register mnemonic port register name p x dd data direction p x af alternate function p x oc output control (open-drain) p x hde high drive enable p x smre stop mode recovery source enable p x pue pull-up enable table 13. port a-c gpio address registers (p x addr) bits 7 6 5 4 3 2 1 0 field paddr[7:0] reset 00h r/w r/w addr fd0h, fd4h, fd8h
ps019707-1003 p r e l i m i n a r y general-purpose i/o z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 41 paddr[7:0]?port address the port address selects one of the sub-regi sters accessible through the port control reg- ister. port a-c control registers the port a-c control registers set the gpio port operation. the va lue in the correspond- ing port a-c address register determines th e control sub-registers accessible using the port a-c control register (table 14). pctl[7:0]?port control the port control register provides access to a ll sub-registers that configure the gpio port operation. paddr[7:0] port control sub-register accessibl e using the port a-c control registers 00h no function. provides so me protection against accident al port reco nfiguration. 01h data direction 02h alternate function 03h output control (open-drain) 04h high drive enable 05h stop mode recovery source enable. 06h pull-up enable 07h-ffh no function. table 14. port a-c control registers (p x ctl) bits 7 6 5 4 3 2 1 0 field pctl reset 00h r/w r/w addr fd1h, fd5h, fd9h
ps019707-1003 p r e l i m i n a r y general-purpose i/o z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 42 port a-c data direction sub-registers the port a-c data direction sub-register is accessed through the port a-c control regis- ter by writing 01h to the port a- c address register (table 15). dd[7:0]?data direction these bits control the direction of the associa ted port pin. port alternate function opera- tion overrides the data direction register setting. 0 = output. data in the port a-c output da ta register is driven onto the port pin. 1 = input. the port pin is sampled and the va lue written into the port a-c input data reg- ister. the output driver is tri-stated. port a-c alternate function sub-registers the port a-c alternate function sub-register (table 16) is accessed through the port a-c control register by writing 02h to the port a-c address register. the port a-c alternate function sub-registers select the alternate fu nctions for the selected pins. refer to the gpio alternate functions section to determine the alte rnate function associated with each port pin. do not enable alternate function for gp io port pins which do not have an associated alternate functi on. failure to follow this guideline may result in unpredictable operation. table 15. port a-c data direction sub-registers bits 7 6 5 4 3 2 1 0 field dd7 dd6 dd5 dd4 dd3 dd2 dd1 dd0 reset 11111111 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr if 01h in port a-c address register, accessible via port a-c control register table 16. port a-c alternat e function sub-registers bits 7 6 5 4 3 2 1 0 field af7af6af5af4af3af2af1af0 reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr if 02h in port a-c address register, accessible via port a-c control register caution:
ps019707-1003 p r e l i m i n a r y general-purpose i/o z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 43 af[7:0]?port alternate function enabled 0 = the port pin is in normal mode and the ddx bit in the port a-c data direction sub-register determines the direction of the pin. 1 = the alternate function is se lected. port pin operation is controlled by the alternate function. port a-c output control sub-registers the port a-c output control sub-register (table 17) is accessed through the port a-c control register by writing 03h to the port a-c address register. setting the bits in the port a-c output control sub-registers to 1 co nfigures the specified port pins for open- drain operation. these sub-registers affect the pi ns directly and, as a result, alternate func- tions are also affected. poc[7:0]?port output control these bits function independently of the a lternate function bit and always disable the drains if set to 1. 0 = the drains are enabled for any output m ode (unless overridden by the alternate func- tion). 1 = the drain of the associated pin is disabled (open-drain mode). table 17. port a-c output control sub-registers bits 7 6 5 4 3 2 1 0 field poc7 poc6 poc5 poc4 poc3 poc2 poc1 poc0 reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr if 03h in port a-c address register, accessible via port a-c control register
ps019707-1003 p r e l i m i n a r y general-purpose i/o z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 44 port a-c high drive enable sub-registers the port a-c high drive enable sub-register (table 18) is accessed through the port a-c control register by writing 04h to the port a-c address register. setting the bits in the port a-c high drive enable sub-registers to 1 configures the specified port pins for high current output drive operation. the port a-c high drive enable sub-register affects the pins directly and, as a result, a lternate functions are also affected. phde[7:0]?port high drive enabled 0 = the port pin is configured fo r standard output current drive. 1 = the port pin is configured for high output current drive. port a-c stop mode recovery source enable sub-registers the port a-c stop mode recovery source enable sub-register (table 19) is accessed through the port a-c control register by writing 05h to the port a-c address register. setting the bits in the port a-c stop mode recovery source enable sub-registers to 1 configures the specified port pins as a stop mode recovery source. during stop mode, any logic transition on a port pin enabled as a stop mode recovery source initiates stop mode recovery. table 18. port a-c high drive enable sub-registers bits 7 6 5 4 3 2 1 0 field phde7 phde6 phde5 phde4 phde3 phde2 phde1 phde0 reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr if 04h in port a-c address register, accessible via port a-c control register
ps019707-1003 p r e l i m i n a r y general-purpose i/o z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 45 psmre[7:0]?port stop mode recovery source enabled 0 = the port pin is not configured as a stop mode recovery source. transitions on this pin during stop mode do not initiate stop mode recovery. 1 = the port pin is configured as a stop mo de recovery source. any logic transition on this pin during stop mode initiates stop mode recovery. port a-c pull-up enable sub-registers the port a-c pull-up enable sub-register (table 20) is accessed through the port a-c control register by writing 06h to the port a-c address register. setting the bits in the port a-c pull-up enable sub-re gisters enables a weak internal resistive pull-up on the specified port pins. table 19. port a-c stop mode reco very source enable sub-registers bits 7 6 5 4 3 2 1 0 field psmre7 psmre6 psmre5 psmre4 psmre3 psmre2 psmre1 psmre0 reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr if 05h in port a-c address register, accessible via port a-c control register
ps019707-1003 p r e l i m i n a r y general-purpose i/o z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 46 ppue[7:0]?port pull-up enabled 0 = the weak pull-up on the port pin is disabled. 1 = the weak pull-up on the port pin is enabled. port a-c input data registers reading from the port a-c input data regist ers (table 21) returns the sampled values from the corresponding port pi ns. the port a-c input data registers are read-only. pin[7:0]?port input data sampled data from the corresponding port pin input. 0 = input data is logical 0 (low). 1 = input data is logical 1 (high). table 20. port a-c pull-up enable sub-registers bits 7 6 5 4 3 2 1 0 field ppue7 ppue6 ppue5 ppue4 ppue3 ppue2 ppue1 ppue0 reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr if 06h in port a-c address register, accessible via port a-c control register table 21. port a-c input data registers (pxin) bits 7 6 5 4 3 2 1 0 field pin7 pin6 pin5 pin4 pin3 pin2 pin1 pin0 reset xxxxxxxx r/w rrrrrrrr addr fd2h, fd6h, fdah
ps019707-1003 p r e l i m i n a r y general-purpose i/o z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 47 port a-c output data register the port a-c output data register (table 22) controls the output data to the pins. pout[7:0]?port output data these bits contain the data to be driven to th e port pins. the values are only driven if the corresponding pin is configured as an output and the pin is not configured for alternate function operation. 0 = drive a logical 0 (low). 1= drive a logical 1 (high). high value is not driven if the drain has been disabled by set- ting the corresponding port outp ut control register bit to 1. table 22. port a-c output data register (p x out) bits 7 6 5 4 3 2 1 0 field pout7 pout6 pout5 pout4 pout3 pout2 pout1 pout0 reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr fd3h, fd7h, fdbh
z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? ps019707-1003 p r e l i m i n a r y interrupt controller 48 interrupt controller overview the interrupt controller on th e z8f082x family products prio ritizes the interrupt requests from the on-chip peripherals and the gpio port pins. the features of the interrupt control- ler include the following: ? 19 unique interrupt vectors: ? 12 gpio port pin interrupt sources ? 7 on-chip peripheral interrupt sources ? flexible gpio interrupts ? 8 selectable rising and falling edge gpio interrupts ? 4 dual-edge interrupts ? 3 levels of individually pr ogrammable interrupt priority ? watch-dog timer can be configured to generate an interrupt interrupt requests (irqs) allow peripheral devi ces to suspend cpu oper ation in an orderly manner and force the cpu to start an interrupt service routine (isr). usually this interrupt service routine is involved with the exchange of data, status information, or control infor- mation between the cpu and the interrupting pe ripheral. when the service routine is com- pleted, the cpu returns to the operation from wh ich it was interrupted. the ez8 cpu supports both vectored and polled interrupt handling. for polled interrupts, the interrupt control has no effe ct on operation. refer to the ez8 cpu user manual for more information regarding interrupt servicing by the ez8 cpu. the ez8 cpu user man- ual is available for download at www.zilog.com . interrupt vector listing table 23 lists all of the interrupts available in order of priority. the interrupt vector is stored with the most significant byte (msb) at the even program memory address and the least significant byte (lsb) at the following odd program memory address.
ps019707-1003 p r e l i m i n a r y interrupt controller z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 49 table 23. interrupt vectors in order of priority priority program memory vector address interrupt source highest 0002h reset (not an interrupt) 0004h watch-dog timer (see the section watch-dog timer on page 75 ) 0006h illegal instruction trap (not an interrupt) 0008h reserved 000ah timer 1 000ch timer 0 000eh uart 0 receiver 0010h uart 0 transmitter 0012h i 2 c 0014h spi 0016h adc 0018h port a7, rising or falling input edge 001ah port a6, rising or falling input edge 001ch port a5, rising or falling input edge 001eh port a4, rising or falling input edge 0020h port a3, rising or falling input edge 0022h port a2, rising or falling input edge 0024h port a1, rising or falling input edge 0026h port a0, rising or falling input edge 0028h reserved 002ah reserved 002ch reserved 002eh reserved 0030h port c3, both input edges 0032h port c2, both input edges 0034h port c1, both input edges lowest 0036h port c0, both input edges
ps019707-1003 p r e l i m i n a r y interrupt controller z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 50 architecture figure 9 illustrates a block diagram of the interrupt controller. figure 9. interrupt controller block diagram operation master interrupt enable the master interrupt enable bit ( irqe ) in the interrupt control register globally enables and disables interrupts. interrupts are globally enabled by any of the following actions: ? execution of an ei (enable interrupt) instruction ? execution of an iret (retur n from interrupt) instruction ? writing a 1 to the irqe bit in the interrupt control register interrupts are globally disabled by any of the following actions: ? execution of a di (disable interrupt) instruction ? ez8 cpu acknowledgement of an interru pt service request from the interrupt controller ? writing a 0 to the irqe bit in the interrupt control register ? reset vector irq request high priority medium priority low priority priority mux interrupt request latches and control port interrupts internal interrupts
ps019707-1003 p r e l i m i n a r y interrupt controller z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 51 ? execution of a trap instruction ? illegal instruction trap interrupt vectors and priority the interrupt controller supports three levels of interrupt pr iority. level 3 is the highest priority, level 2 is the second highest priority , and level 1 is the lowest priority. if all of the interrupts were enabled with identical interrupt priority (all as level 2 interrupts, for example), then interrupt priority would be assi gned from highest to lowest as specified in table 23. level 3 interrupts always have higher priority than level 2 interrupts which, in turn, always have higher prio rity than level 1 interrupts. within each interrupt priority level (level 1, level 2, or level 3), priority is assigned as specified in table 23. reset, watch-dog timer interrupt (if enabled), and i llegal instruction trap always have highest priority. interrupt assertion interrupt sources assert their interrupt requests for only a single system clock period (sin- gle pulse). when the interrupt request is ac knowledged by the ez8 cpu, the correspond- ing bit in the interrupt request register is cl eared until the next interrupt occurs. writing a 0 to the corresponding bit in the interrupt re quest register likewise clears the interrupt request. the following style of coding to clear bits in the interrupt request registers is not recommended. all incoming inte rrupts that are received between execution of the first ldx command and the last ldx command are lost. poor coding style that can result in lost interrupt requests: ldx r0, irq0 and r0, mask ldx irq0, r0 to avoid missing interrupts, the following style of coding to clear bits in the interrupt request 0 register is recommended: good coding style that avoids lost interrupt requests: andx irq0, mask software interrupt assertion program code can generate interrupts directly. writing a 1 to the desired bit in the inter- rupt request register triggers an interrupt ( assuming that interrupt is enabled). when the interrupt request is acknowledged by the ez8 cp u, the bit in the interrupt request register is automatically cleared to 0. caution:
ps019707-1003 p r e l i m i n a r y interrupt controller z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 52 the following style of coding to gene rate software interrupts by setting bits in the interrupt request registers is not recommended. all incoming interrupts that are received between execution of the first ldx command and the last ldx command are lost. poor coding style that can result in lost interrupt requests: ldx r0, irq0 or r0, mask ldx irq0, r0 to avoid missing interrupts, the followin g style of coding to set bits in the interrupt request regist ers is recommended: good coding style that avoids lost interrupt requests: orx irq0, mask interrupt control register definitions for all interrupts other than the watch-dog ti mer interrupt, the interru pt control registers enable individual interrupts, set interrupt priorities, and indicate interrupt requests. interrupt request 0 register the interrupt request 0 (irq0) register (tab le 24) stores the interrupt requests for both vectored and polled interrupts. when a request is presented to the in terrupt controller, the corresponding bit in the irq0 register beco mes 1. if interrupts are globally enabled (vec- tored interrupts), the interrupt controller passe s an interrupt request to the ez8 cpu. if interrupts are globally disabl ed (polled interrupts), the ez8 cpu can read the interrupt request 0 register to determine if any interrupt requests are pending. table 24. interrupt requ est 0 register (irq0) bits 7 6 5 4 3 2 1 0 field reserved t1i t0i u0rxi u0txi i2ci spii adci reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr fc0h caution: note:
ps019707-1003 p r e l i m i n a r y interrupt controller z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 53 reserved?must be 0. t1i?timer 1 interrupt request 0 = no interrupt request is pending for timer 1. 1 = an interrupt request from timer 1 is awaiting service. t0i?timer 0 interrupt request 0 = no interrupt request is pending for timer 0. 1 = an interrupt request from timer 0 is awaiting service. u0rxi?uart 0 receiver interrupt request 0 = no interrupt request is pe nding for the uart 0 receiver. 1 = an interrupt request from the ua rt 0 receiver is awaiting service. u0txi?uart 0 transmitter interrupt request 0 = no interrupt request is pending for the uart 0 transmitter. 1 = an interrupt request from the ua rt 0 transmitter is awaiting service. i 2 ci? i 2 c interrupt request 0 = no interrupt request is pending for the i 2 c. 1 = an interrupt request from the i 2 c is awaiting service. spii?spi interrupt request 0 = no interrupt request is pending for the spi. 1 = an interrupt request from the spi is awaiting service. adci?adc interrupt request 0 = no interrupt request is pending for the analog-to-digital converter. 1 = an interrupt request from the analog-t o-digital converter is awaiting service. interrupt request 1 register the interrupt request 1 (irq1) register (table 25) stores inte rrupt requests for both vec- tored and polled interrupts. when a request is presented to the interrupt controller, the cor- responding bit in the irq1 register becomes 1. if interrupts are globally enabled (vectored interrupts), the interrupt controller passes an in terrupt request to the ez8 cpu. if interrupts are globally disabled (polled interrupts), th e ez8 cpu can read the interrupt request 1 register to determine if any interrupt requests are pending.
ps019707-1003 p r e l i m i n a r y interrupt controller z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 54 pa x i?port a pin x interrupt request 0 = no interrupt request is pending for gpio port a pin x . 1 = an interrupt request from gpio port a pin x is awaiting service. where x indicates the specific gpio port pin number (0 through 7). interrupt request 2 register the interrupt request 2 (irq2) register (table 26) stores inte rrupt requests for both vec- tored and polled interrupts. when a request is presented to the interrupt controller, the cor- responding bit in the irq2 register becomes 1. if interrupts are globally enabled (vectored interrupts), the interrupt controller passes an in terrupt request to the ez8 cpu. if interrupts are globally disabled (polled interrupts), th e ez8 cpu can read the interrupt request 2 register to determine if any interrupt requests are pending. reserved?must be 0. pc x i?port c pin x interrupt request 0 = no interrupt request is pending for gpio port c pin x . 1 = an interrupt request from gpio port c pin x is awaiting service. where x indicates the specific gpio po rt c pin number (0 through 3). table 25. interrupt requ est 1 register (irq1) bits 7 6 5 4 3 2 1 0 field pa7i pa6i pa5i pa4i pa3i pa2i pa1i pa0i reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr fc3h table 26. interrupt requ est 2 register (irq2) bits 7 6 5 4 3 2 1 0 field reserved pc3i pc2i pc1i pc0i reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr fc6h
ps019707-1003 p r e l i m i n a r y interrupt controller z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 55 irq0 enable high a nd low bit registers the irq0 enable high and low bit registers (tables 28 and table 29) form a priority encoded enabling for interrupts in the interrupt request 0 register. priority is generated by setting bits in each register. table 27 d escribes the priority control for irq0. reserved?must be 0. t1enh?timer 1 interrupt re quest enable high bit t0enh?timer 0 interrupt re quest enable high bit u0renh?uart 0 receive interrupt request enable high bit u0tenh?uart 0 transmit interrupt request enable high bit i2cenh?i 2 c interrupt request enable high bit spienh?spi interrupt request enable high bit adcenh?adc interrupt request enable high bit table 27. irq0 enable and priority encoding irq0enh[ x ]irq0enl[ x ] priority description 0 0 disabled disabled 0 1 level 1 low 1 0 level 2 nominal 1 1 level 3 high where x indicates the register bits from 0 through 7. table 28. irq0 enable high bit register (irq0enh) bits 7 6 5 4 3 2 1 0 field reserved t1enh t0enh u0renh u0tenh i2cenh spienh adcenh reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr fc1h
ps019707-1003 p r e l i m i n a r y interrupt controller z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 56 reserved?must be 0. t1enl?timer 1 interrupt request enable low bit t0enl?timer 0 interrupt request enable low bit u0renl?uart 0 receive interru pt request enable low bit u0tenl?uart 0 transmit interrupt request enable low bit i2cenl?i 2 c interrupt request enable low bit spienl?spi interrupt request enable low bit adcenl?adc interrupt request enable low bit irq1 enable high a nd low bit registers the irq1 enable high and low bit registers (tables 31 and table 32) form a priority encoded enabling for interrupts in the interrupt request 1 register. priority is generated by setting bits in each register. table 30 d escribes the priority control for irq1. table 29. irq0 enable low bit register (irq0enl) bits 7 6 5 4 3 2 1 0 field reserved t1enl t0enl u0renl u0tenl i2cenl spienl adcenl reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr fc2h table 30. irq1 enable and priority encoding irq1enh[ x ]irq1enl[ x ] priority description 0 0 disabled disabled 0 1 level 1 low 1 0 level 2 nominal 1 1 level 3 high where x indicates the register bits from 0 through 7.
ps019707-1003 p r e l i m i n a r y interrupt controller z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 57 pa x enh?port a bit[ x ] interrupt request enable high bit pa x enl?port a bit[ x ] interrupt reques t enable low bit irq2 enable high a nd low bit registers the irq2 enable high and low bit registers (tables 34 and table 35) form a priority encoded enabling for interrupts in the interrupt request 2 register. priority is generated by setting bits in each register. table 33 d escribes the priority control for irq2. table 31. irq1 enable high bit register (irq1enh) bits 7 6 5 4 3 2 1 0 field pa7enh pa6enh pa5enh pa4enh pa3enh pa2enh pa1enh pa0enh reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr fc4h table 32. irq1 enable low bit register (irq1enl) bits 7 6 5 4 3 2 1 0 field pa7enl pa6enl pa5enl pa4enl pa3enl pa2enl pa1enl pa0enl reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr fc5h table 33. irq2 enable and priority encoding irq2enh[ x ]irq2enl[ x ] priority description 0 0 disabled disabled 0 1 level 1 low 1 0 level 2 nominal 1 1 level 3 high where x indicates the register bits from 0 through 7.
ps019707-1003 p r e l i m i n a r y interrupt controller z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 58 reserved?must be 0. c3enh?port c3 interrupt request enable high bit c2enh?port c2 interrupt request enable high bit c1enh?port c1 interrupt request enable high bit c0enh?port c0 interrupt request enable high bit reserved?must be 0. c3enl?port c3 interrupt request enable low bit c2enl?port c2 interrupt request enable low bit c1enl?port c1 interrupt request enable low bit c0enl?port c0 interrupt request enable low bit interrupt edge select register the interrupt edge sele ct (irqes) register (table 36) de termines whether an interrupt is generated for the rising edge or falling edge on the selected gpio port input pin. the min- table 34. irq2 enable high bit register (irq2enh) bits 7 6 5 4 3 2 1 0 field reserved c3enh c2enh c1enh c0enh reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr fc7h table 35. irq2 enable low bit register (irq2enl) bits 7 6 5 4 3 2 1 0 field reserved c3enl c2enl c1enl c0enl reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr fc8h
ps019707-1003 p r e l i m i n a r y interrupt controller z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 59 imum pulse width must be grea ter than 1 system clock to guarantee capture of the edge triggered interrupt. edge detection for pulses l ess than 1 system clock are not guaranteed. ies x ?interrupt edge select x 0 = an interrupt request is genera ted on the falling edge of the pa x input. 1 = an interrupt request is genera ted on the rising edge of the pa x input. where x indicates the specific gpio port pin number (0 through 7). interrupt control register the interrupt control (irqctl) register (table 37) contains the master enable bit for all interrupts. irqe?interrupt request enable this bit is set to 1 by execution of an ei (enable interrupts) or iret (interrupt return) instruction, or by a direct register write of a 1 to this bit. it is reset to 0 by executing a di instruction, ez8 cpu acknowledgement of an in terrupt request, reset or by a direct regis- ter write of a 0 to this bit. 0 = interrupts are disabled. 1 = interrupts are enabled. reserved?must be 0. table 36. interrupt edge select register (irqes) bits 7 6 5 4 3 2 1 0 field ies7 ies6 ies5 ies4 ies3 ies2 ies1 ies0 reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr fcdh table 37. interrupt control register (irqctl) bits 7 6 5 4 3 2 1 0 field irqe reserved reset 00000000 r/w r/wrrrrrrr addr fcfh
z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? ps019707-1003 p r e l i m i n a r y timers 60 timers overview these z8f082x family products contain up to two 16-bit reloadable timers that can be used for timing, event counting, or generation of pulse-width modulated (pwm) signals. the timers? features include: ? 16-bit reload counter ? programmable prescaler with prescale values from 1 to 128 ? pwm output generation ? capture and compare capability ? external input pin for timer input, clock ga ting, or capture signal. external input pin signal frequency is limited to a maximum of one-fourth the system clock frequency. ? timer output pin ? timer interrupt in addition to the timers described in this chapter, the baud rate generators for any unused uart, spi, or i 2 c peripherals may also be used to provide basic timing function- ality. refer to the respective serial communica tion peripheral chapters for information on using the baud rate generators as timers. architecture figure 10 illustrates the architecture of the timers.
ps019707-1003 p r e l i m i n a r y timers z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 61 figure 10. timer block diagram operation the timers are 16-bit up-counters. minimum tim e-out delay is set by loading the value 0001h into the timer reload high and low by te registers and setting the prescale value to 1. maximum time-out delay is set by loading the value 0000h into the timer reload high and low byte registers and setting the prescale value to 128. if the timer reaches ffffh , the timer rolls over to 0000h and continues counting. timer operating modes the timers can be configured to operate in the following modes: one-shot mode in one-shot mode, the timer counts up to th e 16-bit reload value stored in the timer reload high and low byte registers. the timer input is the system clock. upon reaching the reload value, the timer generates an interrupt and th e count value in the timer high and low byte registers is reset to 0001h . then, the timer is automatically disabled and stops counting. also, if the timer output alternate function is enabled, the timer output pin changes state for one system clock cycle (from low to high or from high to low) upon timer reload. if 16-bit pwm / compare 16-bit counter with prescaler 16-bit reload register timer control compare compare interrupt, pwm, and timer output control timer timer timer block system timer data block interrupt output control bus clock input gate input capture input
ps019707-1003 p r e l i m i n a r y timers z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 62 it is desired to have the timer output make a permanent state change upon one-shot time- out, first set the tpol bit in the timer control register to the start value before beginning one-shot mode. then, after starting the timer, set tpol to the opposite bit value. the steps for configuring a timer for one-shot mode and initiating the count are as fol- lows: 1. write to the timer control register to: ? disable the timer ? configure the timer for one-shot mode. ? set the prescale value. ? if using the timer output alternate functio n, set the initial output level (high or low). 2. write to the timer high and low byte registers to set the starting count value. 3. write to the timer reload high and low byte registers to set the reload value. 4. if desired, enable the timer interrupt and se t the timer interrupt priority by writing to the relevant interrupt registers. 5. if using the timer output function, configure the associated gpio port pin for the timer output alternate function. 6. write to the timer control register to enable the timer and initiate counting. in one-shot mode, the system clock always provides the timer input. the timer period is given by the following equation: continuous mode in continuous mode, the timer counts up to the 16-bit reload va lue stored in the timer reload high and low byte registers. the timer input is th e system clock. upon reaching the reload value, the timer generate s an interrupt, the count value in the timer high and low byte registers is reset to 0001h and counting resumes. also, if the timer output alternate func tion is enabled, the timer output pin changes state (from low to high or from high to low) upon timer reload. the steps for conf iguring a timer for continuous mo de and initiating the count are as follows: 1. write to the timer control register to: ? disable the timer ? configure the timer for continuous mode. ? set the prescale value. one-shot mode time-out period (s) reload value start value ? () prescale system clock frequency (hz) ------------------------------------------------------------------------------------------------------ =
ps019707-1003 p r e l i m i n a r y timers z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 63 ? if using the timer output alternate functio n, set the initial output level (high or low). 2. write to the timer high and low byte regist ers to set the starting count value (usually 0001h ). this only affects the first pass in continuous mode. after the first timer reload in continuous mode, counting al ways begins at the reset value of 0001h . 3. write to the timer reload high and low byte registers to set the reload value. 4. if desired, enable the timer interrupt and se t the timer interrupt priority by writing to the relevant interrupt registers. 5. if using the timer output function, configure the associated gpio port pin for the timer output alternate function. 6. write to the timer control register to enable the timer and initiate counting. in continuous mode, the system clock alwa ys provides the timer input. the timer period is given by the following equation: if an initial starting value other than 0001h is loaded into the timer high and low byte registers, the one-shot mode equation must be used to determine the first time-out period. counter mode in counter mode, the timer co unts input transitions from a gpio port pin. the timer input is taken from the gpio port pi n timer input alternate function. the tpol bit in the timer control register selects whether the coun t occurs on the rising edge or the falling edge of the timer input signal. in c ounter mode, the prescaler is disabled. the input frequency of the timer inpu t signal must not exceed one-fourth the system clock frequency. upon reaching the reload value stored in the timer reload high and low byte registers, the timer generates an interrupt, the count value in the ti mer high and low byte registers is reset to 0001h and counting resumes. also, if the timer output alternate function is enabled, the timer output pin changes state (from low to high or from high to low) at timer reload. the steps for configuring a timer for coun ter mode and initiating the count are as fol- lows: 1. write to the timer control register to: ? disable the timer ? configure the timer for counter mode. continuous mode time-out period (s) reload value prescale system clock frequency (hz) ---------------------------------------------------------------------------- = caution:
ps019707-1003 p r e l i m i n a r y timers z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 64 ? select either the rising edge or falling edge of the timer input signal for the count. this also sets the initial logic level (hig h or low) for the timer output alternate function. however, the timer output fu nction does not have to be enabled. 2. write to the timer high and low byte regi sters to set the startin g count value. this only affects the first pass in counter mode. after the first timer reload in counter mode, counting always begins at the reset value of 0001h . generally, in counter mode the timer high and low byte registers must be written with the value 0001h . 3. write to the timer reload high and low byte registers to set the reload value. 4. if desired, enable the timer interrupt and se t the timer interrupt priority by writing to the relevant interrupt registers. 5. configure the associated gpio port pi n for the timer input alternate function. 6. if using the timer output function, configure the associated gpio port pin for the timer output alternate function. 7. write to the timer control register to enable the timer. in counter mode, the number of timer input transitions since the timer start is given by the following equation: pwm mode in pwm mode, the timer output s a pulse-width modulator (pwm) output signal through a gpio port pin. the timer input is the system clock. the timer first counts up to the 16- bit pwm match value stored in the timer pw m high and low byte registers. when the timer count value matches the pwm value, th e timer output toggles. the timer continues counting until it reaches the reload value stor ed in the timer reload high and low byte registers. upon reaching the reload value, the timer generates an interrupt, the count value in the timer high and low byte registers is reset to 0001h and counting resumes. if the tpol bit in the timer control register is set to 1, the timer output signal begins as a high (1) and then transitions to a low (0) when the timer value ma tches the pwm value. the timer output signal returns to a high (1 ) after the timer reaches the reload value and is reset to 0001h . if the tpol bit in the timer control register is set to 0, the timer output signal begins as a low (0) and then transitions to a high (1) when the timer value matches the pwm value. the timer output signal returns to a low (0 ) after the timer reaches the reload value and is reset to 0001h . the steps for configuring a timer for pwm mode and initiating the pwm operation are as follows: counter mode timer input transitions current count value start value ? =
ps019707-1003 p r e l i m i n a r y timers z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 65 1. write to the timer control register to: ? disable the timer ? configure the timer for pwm mode. ? set the prescale value. ? set the initial logic level (high or lo w) and pwm high/low transition for the timer output alternate function. 2. write to the timer high and low byte registers to set the starting count value (typically 0001h ). this only affects the first pass in pwm mode. after the first timer reset in pwm mode, counting always begins at the reset value of 0001h . 3. write to the pwm high and low byte registers to set the pwm value. 4. write to the timer reload high and low by te registers to set the reload value (pwm period). the reload value must be greater than the pwm value. 5. if desired, enable the timer interrupt and se t the timer interrupt priority by writing to the relevant interrupt registers. 6. configure the associated gpio port pin for the timer output alternate function. 7. write to the timer control register to enable the timer and initiate counting. the pwm period is given by the following equation: if an initial starting value other than 0001h is loaded into the timer high and low byte registers, the one-shot mode equation must be used to determine the first pwm time-out period. if tpol is set to 0, the ratio of the pwm output high time to the total period is given by: if tpol is set to 1, the ratio of the pwm output high time to the total period is given by: capture mode in capture mode, the current timer count valu e is recorded when the desired external timer input transition occurs. the capture coun t value is written to the timer pwm high and low byte registers. the timer input is the system clock. the tpol bit in the timer control register determines if the capture occurs on a rising edge or a falling edge of the pwm period (s) reload value prescale system clock frequency (hz) ---------------------------------------------------------------------------- = pwm output high time ratio (%) reload value pwm value ? reload value ----------------------------------------------------------------------- - 100 = pwm output high time ratio (%) pwm value reload value ---------------------------------- 100 =
ps019707-1003 p r e l i m i n a r y timers z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 66 timer input signal. when the capture event occu rs, an interrupt is generated and the timer continues counting. the timer continues coun ting up to the 16-bit reload valu e stored in the timer reload high and low byte registers. upon reaching the reload value, th e timer generates an interrupt and continues counting. the steps for configuring a timer for captur e mode and initiating the count are as fol- lows: 1. write to the timer control register to: ? disable the timer ? configure the timer for capture mode. ? set the prescale value. ? set the capture edge (rising or falling) for the timer input. 2. write to the timer high and low byte registers to set the starting count value (typically 0001h ). 3. write to the timer reload high and low byte registers to set the reload value. 4. clear the timer pwm high and low byte registers to 0000h . this allows user software to determine if interrupts were generated by either a capture event or a reload. if the pwm high and lo w byte registers still contain 0000h after the interrupt, then the interrupt was generated by a reload. 5. if desired, enable the timer interrupt and se t the timer interrupt priority by writing to the relevant interrupt registers. 6. configure the associated gpio port pi n for the timer input alternate function. 7. write to the timer control register to enable the timer and initiate counting. in capture mode, the elapsed time from timer start to capture event can be calculated using the following equation: compare mode in compare mode, the timer counts up to the 16-bit maximum compare value stored in the timer reload high and low byte registers. the timer input is th e system clock. upon reaching the compare value, the timer genera tes an interrupt and co unting continues (the timer value is not reset to 0001h ). also, if the timer output alternate function is enabled, the timer output pin changes state (from low to high or from high to low) upon com- pare. capture elapsed time (s) capture value start value ? () prescale system clock frequency (hz) --------------------------------------------------------------------------------------------------------- =
ps019707-1003 p r e l i m i n a r y timers z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 67 if the timer reaches ffffh , the timer rolls over to 0000h and continue counting. the steps for configuring a timer for compar e mode and initiating th e count are as fol- lows: 1. write to the timer control register to: ? disable the timer ? configure the timer for compare mode. ? set the prescale value. ? set the initial logic level (high or low) fo r the timer output alternate function, if desired. 2. write to the timer high and low byte registers to set the starting count value. 3. write to the timer reload high and low byte registers to set the compare value. 4. if desired, enable the timer interrupt and se t the timer interrupt priority by writing to the relevant interrupt registers. 5. if using the timer output function, configure the associated gpio port pin for the timer output alternate function. 6. write to the timer control register to enable the timer and initiate counting. in compare mode, the system clock always pr ovides the timer inpu t. the compare time is given by the following equation: gated mode in gated mode, the timer counts only when the timer input si gnal is in its active state (asserted), as determined by the tpol bit in the timer control register. when the timer input signal is asserted, counting begins. a timer interrupt is generated when the timer input signal is deasserted or a timer reload occurs. to determine if a timer input signal deassertion generated the interrupt, read the as sociated gpio input value and compare to the value stored in the tpol bit. the timer counts up to the 16 -bit reload value stored in th e timer reload high and low byte registers. the timer input is the system clock. when r eaching the relo ad value, the timer generates an interrupt, the count value in the timer high and low byte registers is reset to 0001h and counting resumes (assuming the ti mer input signal is still asserted). also, if the timer output alternate function is enabled, the timer output pin changes state (from low to high or from hi gh to low) at timer reset. the steps for configuring a tim er for gated mode and initiatin g the count are as follows: 1. write to the timer control register to: ? disable the timer compare mode time (s) compare value start value ? () prescale system clock frequency (hz) ------------------------------------------------------------------------------------------------------------ =
ps019707-1003 p r e l i m i n a r y timers z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 68 ? configure the timer for gated mode. ? set the prescale value. 2. write to the timer high and low byte regi sters to set the startin g count value. this only affects the first pass in gated mode. after the first timer reset in gated mode, counting always begins at the reset value of 0001h . 3. write to the timer reload high and low byte registers to set the reload value. 4. if desired, enable the timer interrupt and se t the timer interrupt priority by writing to the relevant interrupt registers. 5. configure the associated gpio port pi n for the timer input alternate function. 6. write to the timer control register to enable the timer. 7. assert the timer input signal to initiate the counting. capture/compare mode in capture/compare mode, the timer begins counting on the first external timer input transition. the desired transition (ri sing edge or falling edge) is set by the tpol bit in the timer control register. the timer input is the system clock. every subsequent desired transitio n (after the first) of the timer input signal captures the current count value. the capture value is wr itten to the timer pwm high and low byte registers. when the capture even t occurs, an interrupt is gene rated, the count value in the timer high and low byte registers is reset to 0001h , and counting resumes. if no capture event occurs, the timer counts up to the 16-bit compare value stored in the timer reload high and low byte registers. up on reaching the compare value, the timer generates an interrupt, the count value in the timer high and low byte registers is reset to 0001h and counting resumes. the steps for configuring a timer for capture/compare mode and initiating the count are as follows: 1. write to the timer control register to: ? disable the timer ? configure the timer for capture/compare mode. ? set the prescale value. ? set the capture edge (rising or falling) for the timer input. 2. write to the timer high and low byte registers to set the starting count value (typically 0001h ). 3. write to the timer reload high and low byte registers to set the compare value. 4. if desired, enable the timer interrupt and se t the timer interrupt priority by writing to the relevant interrupt registers.
ps019707-1003 p r e l i m i n a r y timers z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 69 5. configure the associated gpio port pi n for the timer input alternate function. 6. write to the timer control register to enable the timer. 7. counting begins on the first appropriate transition of the timer input signal. no interrupt is generated by this first edge. in capture/compare mode, the elapsed time from timer start to capture event can be calculated using the following equation: reading the timer count values the current count va lue in the timers can be read while counting (enabled). this capability has no effect on timer operation. when the timer is enabled and the timer high byte reg- ister is read, the contents of the timer low byte register are placed in a holding register. a subsequent read from the timer low byte register returns the value in the holding register. this operation allows accurate reads of the full 16-bit time r count value while enabled. when the timers are not enabled, a read fro m the timer low byte register returns the actual value in the counter. timer output signal operation timer output is a gpio port pin alternate func tion. generally, the timer output is toggled every time the counter is reloaded. timer control register definitions timer 0-1 high and low byte registers the timer 0-1 high and low byte (txh and tx l) registers (tables 38 and 39) contain the current 16-bit timer count value. when the tim er is enabled, a read from txh causes the value in txl to be stored in a temporary holding register. a read from tmrl always returns this temporary register when the timers are enabled. when the timer is disabled, reads from the tmrl reads the register directly. writing to the timer high and low byte regist ers while the timer is enabled is not recom- mended. there are no temporary holding regist ers available for write operations, so simul- taneous 16-bit writes are not possible. if eith er the timer high or low byte registers are capture elapsed time (s) capture value start value ? () prescale system clock frequency (hz) --------------------------------------------------------------------------------------------------------- =
ps019707-1003 p r e l i m i n a r y timers z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 70 written during counting, the 8- bit written value is placed in the counter (high or low byte) at the next clock edge. the counte r continues counting from the new value. th and tl?timer high and low bytes these 2 bytes, {tmrh[7:0], tmrl[7:0]}, cont ain the current 16-bit timer count value. timer reload high and low byte registers the timer 0-1 reload high and low byte (txrh and txrl) registers (tables 40 and 41) store a 16-bit reload value, {trh[7:0], trl[ 7:0]}. values written to the timer reload high byte register are stored in a temporar y holding register. when a write to the timer reload low byte register occurs, the temporar y holding register value is written to the timer high byte register. this operation a llows simultaneous updates of the 16-bit timer reload value. table 38. timer 0-1 high byte register (txh) bits 7 6 5 4 3 2 1 0 field th reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr f00h, f08h table 39. timer 0-1 low byte register (txl) bits 7 6 5 4 3 2 1 0 field tl reset 00000001 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr f01h, f09h
ps019707-1003 p r e l i m i n a r y timers z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 71 in compare mode, the timer reload high and low byte registers store the 16-bit compare value. trh and trl?timer reload register high and low these two bytes form the 16-bit reload value, {trh[7:0], trl[ 7:0]}. this value sets the maximum count value which in itiates a timer reload to 0001h . in compare mode, these two byte form the 16-bit compare value. table 40. timer 0-1 reload high byte register (txrh) bits 7 6 5 4 3 2 1 0 field trh reset 11111111 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr f02h, f0ah table 41. timer 0-1 reload low byte register (txrl) bits 7 6 5 4 3 2 1 0 field trl reset 11111111 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr f03h, f0bh
ps019707-1003 p r e l i m i n a r y timers z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 72 timer 0-1 pwm high and low byte registers the timer 0-1 pwm high and low byte (t xpwmh and txpwml) registers (tables 42 and 43) are used for pulse-width modulator (p wm) operations. these registers also store the capture values for the capture and capture/compare modes. pwmh and pwml?pulse-width mo dulator high and low bytes these two bytes, {pwmh[7:0], pwml[7:0]}, form a 16-bit value that is compared to the current 16-bit timer count. when a match oc curs, the pwm output changes state. the pwm output value is set by the tpol bit in the timer control register (txctl) register. the txpwmh and txpwml registers also st ore the 16-bit captured timer value when operating in capture or capture/compare modes. table 42. timer 0-1 pwm high byte register (txpwmh) bits 7 6 5 4 3 2 1 0 field pwmh reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr f04h, f0ch table 43. timer 0-1 pwm low byte register (txpwml) bits 7 6 5 4 3 2 1 0 field pwml reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr f05h, f0dh
ps019707-1003 p r e l i m i n a r y timers z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 73 timer 0-3 control 0 registers the timer 0-3 control 0 (txctl0) registers (tables 44 and 45) allow cascading of the timers. csc?cascade timers 0 = timer input signal comes from the pin. 1 = for timer 0, input signal is connected to timer 1 output. for timer 1, input signal is connected to timer 0 output. timer 0-1 control 1 registers the timer 0-1 control (txctl) registers enab le/disable the timers, set the prescaler value, and determine the timer operating mode. ten?timer enable 0 = timer is disabled. 1 = timer enabled to count. tpol?timer input/output polarity operation of this bit is a function of the current operating mode of the timer. one-shot mode when the timer is disabled, the timer output signal is set to the value of this bit. table 44. timer 0-3 control 0 register (txctl0) bits 7 6 5 4 3 2 1 0 field reserved csc reserved reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr f06h, f0eh, f16h, f1eh table 45. timer 0-1 control register (txctl) bits 7 6 5 4 3 2 1 0 field ten tpol pres tmode reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr f07h, f0fh
ps019707-1003 p r e l i m i n a r y timers z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 74 when the timer is enabled, the timer outp ut signal is complemented upon timer reload. continuous mode when the timer is disabled, the timer output signal is set to the value of this bit. when the timer is enabled, the timer outp ut signal is complemented upon timer reload. counter mode when the timer is disabled, the timer output signal is set to the value of this bit. when the timer is enabled, the timer outp ut signal is complemented upon timer reload. pwm mode 0 = timer output is forced low (0) when the timer is disabled. when enabled, the timer output is forced hi gh (1) upon pwm count matc h and forced low (0) upon reload. 1 = timer output is forced high (1) when the timer is disabled. when enabled, the timer output is forced low (0) upon pwm count match and forced high (1) upon reload. capture mode 0 = count is captured on the rising edge of the timer input signal. 1 = count is captured on the fallin g edge of the timer input signal. compare mode when the timer is disabled, the timer output signal is set to the value of this bit. when the timer is enabled, the timer outp ut signal is complemented upon timer reload. gated mode 0 = timer counts when the timer input signal is high (1) and interrupts are generated on the falling edge of the timer input. 1 = timer counts when the ti mer input signal is low (0) and interrupts are generated on the rising edge of the timer input. capture/compare mode 0 = counting is started on the first rising edge of the timer input signal. the current count is captured on subsequent risi ng edges of the timer input signal. 1 = counting is started on the first falling ed ge of the timer input signal. the current count is captured on subsequent fa lling edges of the timer input signal. pres?prescale value. the timer input clock is divided by 2 pres , where pres can be set from 0 to 7. the prescaler is reset each time the timer is disabled. this insures proper clock division
ps019707-1003 p r e l i m i n a r y timers z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 75 each time the timer is restarted. 000 = divide by 1 001 = divide by 2 010 = divide by 4 011 = divide by 8 100 = divide by 16 101 = divide by 32 110 = divide by 64 111 = divide by 128 tmode?timer mode 000 = one-shot mode 001 = continuous mode 010 = counter mode 011 = pwm mode 100 = capture mode 101 = compare mode 110 = gated mode 111 = capture/compare mode
z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? ps019707-1003 p r e l i m i n a r y watch-dog timer 75 watch-dog timer overview the watch-dog timer (wdt) help s protect against corrupt or unreliable software, power faults, and other system-level problems whic h may place the z8f082x family device into unsuitable operating states. the watch-do g timer includes the following features: ? on-chip rc oscillator ? a selectable time-out response: reset or interrupt ? 24-bit programmable time-out value operation the watch-dog timer (wdt) is a retriggerable on e-shot timer that resets or interrupts the z8f082x family device when the wdt reaches its terminal count. the watch-dog timer uses its own dedicated on-chip rc oscillator as its clock source. the watch-dog timer has only two modes of operation?on and off. once enabled, it always counts and must be refreshed to prevent a time-out. an enab le can be performed by executing the wdt instruction or by setting the wdt_ao option bit. the wdt_ao bit enables the watch-dog timer to operate all the time, even if a wdt instruction has not been executed. the watch-dog timer is a 24-bit reloadable do wncounter that uses three 8-bit registers in the ez8 cpu register space to set the reload value. the nominal wdt time-out period is given by the following equation: where the wdt reload value is the deci mal value of the 24-bit value given by {wdtu[7:0], wdth[7:0], wdtl[7:0]} and th e typical watch-dog timer rc oscillator frequency is 10khz. the watch-dog timer cannot be refreshed once it reaches 000002h . the wdt reload value must no t be set to values below 000004h . table 45 provides wdt time-out period (ms) wdt reload value 10 ----------------- ------------------ -------------- - =
ps019707-1003 p r e l i m i n a r y watch-dog timer z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 76 information on approximate time-out delays for the minimum and maximum wdt reload values. watch-dog timer refresh when first enabled, the watch-dog timer is loaded with the value in the watch-dog timer reload registers. the watch- dog timer then counts down to 000000h unless a wdt instruction is executed by the ez8 cp u. execution of the wdt instruction causes the downcounter to be reloaded with the wdt reload value stored in the watch-dog timer reload registers. counting r esumes following the reload operation. when the z8f082x family device is oper ating in debug mode (using the on-chip debugger), the watch-dog timer is continuous ly refreshed to prevent spurious watch- dog timer time-outs. watch-dog timer time-out response the watch-dog timer times out when the counter reaches 000000h . a time-out of the watch-dog timer generates either an interrupt or a reset. the wdt_res option bit determines the time-out response of th e watch-dog timer. refer to the option bits chap- ter for information regard ing programming of the wdt_res option bit. wdt interrupt in normal operation if configured to generate an interrupt when a time-out occurs, the watch-dog timer issues an interrupt request to the in terrupt controller and sets the wdt status bit in the watch-dog timer control register. if interrupts are enable d, the ez8 cpu respon ds to the interrupt request by fetching the watch-dog timer interrupt vector and executing code from the vector address. after time-out and interrupt generation, the watch-dog timer counter rolls over to its maximum value of fffffh and continues counting. the watch-dog timer counter is not automatically returned to its reload value. wdt reset in stop mode if enabled in stop mode and configured to ge nerate a reset when a time-out occurs and the device is in stop mode, the watch-dog timer initiates a stop mode recovery. both the wdt status bit and the stop bit in the watch-dog timer control register are set to 1 following wdt time-out in stop mode. refer to the reset and stop mode recovery table 45. watch-dog timer approximate time-out delays wdt reload value wdt reload value approximate time-out delay (with 10khz typical wdt oscillator frequency) (hex) (decimal) typical description 000004 4 400 s minimum time-out delay ffffff 16,777,215 1677.5s maximum time-out delay
ps019707-1003 p r e l i m i n a r y watch-dog timer z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 77 chapter for more information. default operation is for the wd t and its rc oscillator to be enabled during stop mode. to minimize power consumption in stop mode , the wdt and its rc oscillator can be dis- abled in stop mode. the following sequenc e configures the wdt to be disabled when the z8f082x family device enters stop mode following execution of a stop instruction: 1. write 55h to the watch-dog timer co ntrol register (wdtctl). 2. write aah to the watch-dog timer co ntrol register (wdtctl). 3. write 81h to the watch-dog timer control re gister (wdtctl) to configure the wdt and its oscillator to be disabled during stop mode. alternatively, write 00h to the watch-dog timer control register (wdtct l) as the third step in this sequence to reconfigure the wdt and its oscillator to be enabled during stop mode. this sequence only affects wdt operation in stop mode. wdt reset in normal operation if configured to generate a re set when a time-out occurs, th e watch-dog timer forces the device into the reset state. the wdt status bit in the watch-dog timer control register is set to 1. refer to the reset and stop mode recovery chapter for more information on reset. wdt reset in stop mode if enabled in stop mode and configured to ge nerate a reset when a time-out occurs and the device is in stop mode, the watch-dog timer initiates a stop mode recovery. both the wdt status bit and the stop bit in the watch-dog timer control register are set to 1 following wdt time-out in stop mode. refer to the reset and stop mode recovery chapter for more information. default operation is for the wd t and its rc oscillator to be enabled during stop mode. to minimize power consumption in stop mode , the wdt and its rc oscillator can be dis- abled in stop mode. the following sequenc e configures the wdt to be disabled when the z8f082x family device enters stop mode following execution of a stop instruction: 1. write 55h to the watch-dog timer co ntrol register (wdtctl). 2. write aah to the watch-dog timer co ntrol register (wdtctl). 3. write 81h to the watch-dog timer control re gister (wdtctl) to configure the wdt and its oscillator to be disabled during stop mode. alternatively, write 00h to the watch-dog timer control register (wdtct l) as the third step in this sequence to reconfigure the wdt and its oscillator to be enabled during stop mode. this sequence only affects wdt operation in stop mode.
ps019707-1003 p r e l i m i n a r y watch-dog timer z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 78 watch-dog timer reload unlock sequence writing the unlock sequence to the watch-dog timer (wdtctl) control register address unlocks the three watch-dog timer reload byte registers (wdtu, wdth, and wdtl) to allow changes to the time- out period. these write operations to the wdtctl register address produce no effect on the bits in the wdtctl register. the locking mechanism prevents spurious writes to the reload registers. the follow se quence is required to unlock the watch-dog timer reload byte regist ers (wdtu, wdth, and wdtl) for write access. 1. write 55h to the watch-dog timer control register (wdtctl). 2. write aah to the watch-dog timer control register (wdtctl). 3. write the watch-dog timer reload upper byte register (wdtu). 4. write the watch-dog timer reload high byte register (wdth). 5. write the watch-dog timer reload low byte register (wdtl). all three watch-dog timer reload registers must be written in the order just listed. there must be no other register writes between each of these operations. if a register write occurs, the lock state machine resets and no fu rther writes can occur, unless the sequence is restarted. the value in the watch-dog timer reload registers is loaded into the counter when the watch-dog timer is first enabled an d every time a wdt instruction is executed. watch-dog timer control register definitions watch-dog timer control register the watch-dog timer control (w dtctl) register, detailed in table 46, is a read-only register that indicates the source of the most recent reset event, indicates a stop mode recovery event, and indicates a watch-dog ti mer time-out. reading this register resets the upper four bits to 0. writing the 55h , aah unlock sequence to the watch- dog timer control (wdtctl) reg- ister address unlocks the three watch-dog ti mer reload byte registers (wdtu, wdth, and wdtl) to allow changes to the time-out period. these write operations to the
ps019707-1003 p r e l i m i n a r y watch-dog timer z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 79 wdtctl register address produce no effect on the bits in the wdtctl register. the locking mechanism preven ts spurious writes to the reload registers. por?power-on reset indicator if this bit is set to 1, a power-on reset event occurred. this bit is reset to 0 if a wdt time- out or stop mode recovery occurs. this bit is also reset to 0 when the register is read. stop?stop mode recovery indicator if this bit is set to 1, a stop mode recovery occurred. if the stop and wdt bits are both set to 1, the stop mode recovery occurred due to a wdt time-out. if the stop bit is 1 and the wdt bit is 0, the stop mode recovery was not caused by a wdt time-out. this bit is reset by a power-on reset or a wdt time-out that occurred while not in stop mode. reading this register also resets this bit. wdt?watch-dog timer time-out indicator if this bit is set to 1, a wdt time-out occurred. a power-on reset resets this pin. a stop mode recovery from a change in an input pin also resets this bit. reading this register resets this bit. ext?external reset indicator if this bit is set to 1, a reset initiated by the external reset pin occurred. a power-on reset or a stop mode recovery from a change in an input pin resets this bit. reading this register resets this bit. table 46. watch-dog timer control register (wdtctl) bits 7 6 5 4 3 2 1 0 field por stop wdt ext reserved reset see descriptions below 0 0 0 0 0 r/w rrrrrrrr addr ff0h reset or stop mode recovery event por stop wdt ext power-on reset 1000 reset via reset pin assertion 0001 reset via watch-dog timer time-out 0010 reset via the on-chip debugger (octctl[1] set to 1) 1000 reset from stop mode through the dbg pin driven low1000 stop mode recovery via gpio pin transition 0100 stop mode recovery via watch-dog timer time-out 0110
ps019707-1003 p r e l i m i n a r y watch-dog timer z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 80 reserved these bits are reserved and must be 0. watch-dog timer reload upper, high and low byte registers the watch-dog timer reload upper, high and low byte (wdtu, wdth, wdtl) reg- isters (tables 47 through 49) form the 24-bit re load value that is lo aded into the watch- dog timer when a wdt instruction executes . the 24-bit reload value is {wdtu[7:0], wdth[7:0], wdtl[7:0]}. writing to these regi sters sets the desired reload value. read- ing from these registers returns the current watch-dog timer count value. the 24-bit wdt reload value must not be set to a value less than 000004h . wdtu?wdt reload upper byte most significant byte (msb), bits[23: 16], of the 24-bit wdt reload value. table 47. watch-dog timer reload upper byte register (wdtu) bits 7 6 5 4 3 2 1 0 field wdtu reset 11111111 r/w r/w* r/w* r/w* r/w* r/w* r/w* r/w* r/w* addr ff1h r/w* - read returns the current wdt count va lue. write sets the desired reload value. table 48. watch-dog timer reload high byte register (wdth) bits 7 6 5 4 3 2 1 0 field wdth reset 11111111 r/w r/w* r/w* r/w* r/w* r/w* r/w* r/w* r/w* addr ff2h r/w* - read returns the curr ent wdt count value. write sets the desired reload value. caution:
ps019707-1003 p r e l i m i n a r y watch-dog timer z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 81 wdth?wdt reload high byte middle byte, bits[15:8], of the 24-bit wdt reload value. wdtl?wdt reload low least significant byte (lsb), bits[7 :0], of the 24-bit wdt reload value. table 49. watch-dog timer reload low byte register (wdtl) bits 7 6 5 4 3 2 1 0 field wdtl reset 11111111 r/w r/w* r/w* r/w* r/w* r/w* r/w* r/w* r/w* addr ff3h r/w* - read returns the curr ent wdt count value. write sets the desired reload value.
ps019707-1003 p r e l i m i n a r y uart z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 81 uart overview the universal asynchronous receiver/transmitter (uart) is a full-duplex communica- tion channel capable of handling asynchronous data transfers. the uart uses a single 8-bit data mode with selectable parity. features of the uart include: ? 8-bit asynchronous data transfer ? selectable even- and odd-parity generation and checking ? option of one or two stop bits ? separate transmit and receive interrupts ? framing, parity, overrun and break detection ? separate transmit and receive enables ? 16-bit baud rate generator (brg) ? selectable multiprocessor (9-bit) mode w ith three configurable interrupt schemes ? baud rate generator timer mode ? driver enable output for external bus transceivers architecture the uart consists of three primary functional blocks: transmitter, rece iver, and baud rate generator. the uart?s transmitter and receiv er function independently, but employ the same baud rate and data format. figure 1 1 illustrates the uart architecture.
ps019707-1003 p r e l i m i n a r y uart z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 82 operation data format the uart always transmits and receives data in an 8-bit data format, least-significant bit first. an even or odd parity bit can be optio nally added to the data stream. each character begins with an active low start bit and ends with either 1 or 2 active high stop bits. figure 11. uart block diagram receive shifter receive data transmit data transmit shift txd rxd system bus parity checker parity generator receiver control control registers transmitter control cts status register register register register baud rate generator de with address compare
ps019707-1003 p r e l i m i n a r y uart z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 83 figures 12 and 13 illustrates the asynchronous data format employed by the uart with- out parity and with parity, respectively. transmitting data using the polled method follow these steps to transmit data us ing the polled method of operation: 1. write to the uart baud rate high and lo w byte registers to set the desired baud rate. 2. enable the uart pin functions by config uring the associated gpio port pins for alternate function operation. 3. if multiprocessor mode is desired, write to the uart control 1 register to enable multiprocessor (9-bit) mode functions. ? set the multiprocessor mode select ( mpen ) to enable multiprocessor mode. 4. write to the uart control 0 register to: ? set the transmit enable bit ( ten ) to enable the uart for data transmission ? if parity is desired and multiprocessor mode is not enabled, set the parity enable bit ( pen ) and select either even or odd parity ( psel ). figure 12. uart asynchronous data format without parity figure 13. uart asynchronous data format with parity start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 data field lsb msb idle state of line stop bit(s) 1 2 1 0 start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity data field lsb msb idle state of line stop bit(s) 1 2 1 0
ps019707-1003 p r e l i m i n a r y uart z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 84 ? set or clear the ctse bit to enable or disable control from the remote receiver using the cts pin. 5. check the tdre bit in the uart status 0 register to determine if the transmit data register is empty (indicated by a 1). if empty, continue to step 6. if the transmit data register is full (indicated by a 0), continue to monitor the tdre bit until the transmit data register becomes available to receive new data. 6. write the uart control 1 register to select the outgoing address bit. ? set the multiprocessor bit transmitter ( mpbt ) if sending an address byte, clear it if sending a data byte. 7. write the data byte to the uart transmit data register. the transmitter automatically transfers the data to the transmit sh ift register and transmits the data. 8. if desired and multiprocessor mode is enabled, make any changes to the multiprocessor bit transmitter (mpbt) value. 9. to transmit additional bytes, return to step 5. transmitting data using th e interrupt-driven method the uart transmitter interrupt indicates the ava ilability of the transmit data register to accept new data for transmission. follow these steps to configure the uart for interrupt- driven data transmission: 1. write to the uart baud rate high and lo w byte registers to set the desired baud rate. 2. enable the uart pin functions by config uring the associated gpio port pins for alternate function operation. 3. execute a di instruction to disable interrupts. 4. write to the interrupt control registers to enable the uart transmitter interrupt and set the desired priority. 5. if multiprocessor mode is desired, write to the uart control 1 register to enable multiprocessor (9-bit) mode functions. ? set the multiprocessor mode select ( mpen ) to enable multiprocessor mode. 6. write to the uart control 0 register to: ? set the transmit enable bit ( ten ) to enable the uart for data transmission ? enable parity, if desired and if multipro cessor mode is not enabled, and select either even or odd parity. ? set or clear the ctse bit to enable or disable control from the remote receiver via the cts pin. 7. execute an ei instruc tion to enable interrupts.
ps019707-1003 p r e l i m i n a r y uart z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 85 the uart is now configured for interrupt-d riven data transmission. because the uart transmit data register is empty, an interr upt is generated immediately. when the uart transmit interrupt is detected, the associated interrupt service routine (isr) performs the following: 1. write the uart control 1 register to select the outgoing address bit: ? set the multiprocessor bit transmitter ( mpbt ) if sending an address byte, clear it if sending a data byte. 2. write the data byte to the uart transmit data register. the transmitter automatically transfers the data to the transmit sh ift register and transmits the data. 3. clear the uart transmit interrupt bit in th e applicable interrupt request register. 4. execute the iret instruction to return from the interrupt-s ervice routine and wait for the transmit data register to again become empty. receiving data using the polled method follow these steps to configure th e uart for polled data reception: 1. write to the uart baud rate high and lo w byte registers to set the desired baud rate. 2. enable the uart pin functions by config uring the associated gpio port pins for alternate function operation. 3. write to the uart control 1 register to enable multiprocessor mode functions, if desired. 4. write to the uart control 0 register to: ? set the receive enable bit ( ren ) to enable the uart for data reception ? enable parity, if desired and if multipro cessor mode is not enabled, and select either even or odd parity. 5. check the rda bit in the uart status 0 register to determine if the receive data register contains a valid data byte (indicated by a 1). if rda is set to 1 to indicate available data, continue to step 5. if the rece ive data register is empty (indicated by a 0), continue to monitor the rda bit awaiting reception of the valid data. 6. read data from the uart receive data re gister. if operating in multiprocessor (9-bit) mode, further actions may be required depe nding on the multip rocessor mode bits mpmd[1:0]. 7. return to step 4 to receive additional data. receiving data using the interrupt-driven method the uart receiver interrupt indicates the av ailability of new data (as well as error con- ditions). follow these steps to configure the uart receiver for interrupt-driven operation:
ps019707-1003 p r e l i m i n a r y uart z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 86 1. write to the uart baud rate high and lo w byte registers to set the desired baud rate. 2. enable the uart pin functions by config uring the associated gpio port pins for alternate function operation. 3. execute a di instruction to disable interrupts. 4. write to the interrupt control registers to enable the uart receiver interrupt and set the desired priority. 5. clear the uart receiver interrupt in th e applicable interrupt request register. 6. write to the uart control 1 register to enable multiprocessor (9-bit) mode functions, if desired. ? set the multiprocessor mode select ( mpen ) to enable multiprocessor mode. ? set the multiprocessor mode bits, mpmd[1:0], to select the desired address matching scheme. ? configure the uart to interrupt on received data and errors or errors only (interrupt on errors only is unlikely to be useful for z8 encore! devices without a dma block) 7. write the device address to the address compare register (aut omatic multiprocessor modes only). 8. write to the uart control 0 register to: ? set the receive enable bit ( ren ) to enable the uart for data reception ? enable parity, if desired and if multipro cessor mode is not enabled, and select either even or odd parity. 9. execute an ei instruc tion to enable interrupts. the uart is now configured for interrupt-driven data reception. when the uart receiver interrupt is detected, the associat ed interrupt service rou tine (isr) performs the following: 1. check the uart status 0 register to dete rmine the source of the interrupt - error, break, or received data. 2. if the interrupt was due to data available, read the data from the uart receive data register. if operating in multiprocessor (9-b it) mode, further actions may be required depending on the multiproces sor mode bits mpmd[1:0]. 3. clear the uart receiver interrupt in th e applicable interrupt request register. 4. execute the iret instruction to return from the interrupt -service routine and await more data.
ps019707-1003 p r e l i m i n a r y uart z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 87 clear to send (cts ) operation the cts pin, if enabled by the ctse bit of the uart control 0 register, performs flow control on the outgoing transmit datastream. the clear to send (cts ) input pin is sam- pled one system clock before beginning any new character transmission. to delay trans- mission of the next data character, an external receiver must deassert cts at least one system clock cycle before a new data transm ission begins. for multiple character trans- missions, this would typically be done during stop bit transmission. if cts deasserts in the middle of a character transmission, the current character is sent completely. multiprocessor (9-bit) mode the uart has a multiprocessor (9-bit) mode th at uses an extra (9th) bit for selective communication when a number of processors share a common uart bus. in multiproces- sor mode (also referred to as 9-bit mode), the multiprocessor bit (mp) is transmitted immediately following the 8-bits of data an d immediately preceding the stop bit(s) as illustrated in figure 14. the character format is: in multiprocessor (9-bit) mode , the parity bit location (9th bit) becomes the multiproces- sor control bit. the uart control 1 and status 1 registers provide multiprocessor (9-bit) mode control and status inform ation. if an automatic address matching scheme is enabled, the uart address compare register holds the network address of the device. multiprocessor (9-bit) mode receive interrupts when multiprocessor mode is en abled, the uart will only pro cess frames addressed to it. the determination of whether a frame of data is addressed to the uart can be made in hardware, software or some combination of the two, depe nding on the multiprocessor con- figuration bits. in general, the address compar e feature reduces the load on the cpu, since it does not need to access the uart when it receiv es data directed to other devices on the multi-node network. the following three multi- processor modes are available in hard- ware: ? interrupt on all address bytes figure 14. uart asynchronous mu ltiprocessor mode data format start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 mp data field lsb msb idle state of line stop bit(s) 1 2 1 0
ps019707-1003 p r e l i m i n a r y uart z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 88 ? interrupt on matched address bytes and correctly framed data bytes ? interrupt only on corre ctly framed data bytes these modes are selected with mpmd[1:0] in the uart control 1 register. for all mul- tiprocessor modes, bit mpen of the uart control 1 register must be set to 1. the first scheme is enabled by writing 01b to mpmd[1:0] . in this mode, all incoming address bytes cause an interrupt, while data bytes never cause an interrupt. the interrupt service routine must manually check the addre ss byte that caused triggered the interrupt. if it matches the uart address, the software should clear mpmd[0] . at this point, each new incoming byte will interrupt the cpu. the software is then resp onsible for determin- ing the end of the frame. it will check for this by reading the mprx bit of the uart status 1 register for each incoming byte. if mprx =1, then a new frame has begun. if the address of this new frame is differen t from the uart?s address, then mpmd[0] should be set to 1 causing the uart interrupts to go inactive un til the next address byte. if the new frame?s address matches the uart?s, then the data in the new frame should be processed as well. setting mpmd[1:0] to 10b and writing the uart?s address into th e uart address compare register. this mode introduces mo re hardware control, interrupting only on frames that match the uart?s address. when an incoming address byte does not match the uart?s address, it is ignored. all successive data bytes in this frame are also ignored. when a matching address byte o ccurs, an interrupt is issued and further interrupts will now occur on each succesive data byte. the fi rst data byte in the frame will have the newfrm =1 in the uart status 1 register. when the next address byte occurs, the hard- ware will compare it to the uart?s address. if there is a match, the interrupts will con- tinue and the newfrm bit will be set for the first byte of the new frame. if there is no match, then the uart to ignore all inco ming bytes until the next address match. the third scheme is enabled by setting mpmd[1:0] to 11b and by writing the uart?s address into the uart address co mpare register. this mode is identical to the second scheme, except that there are no interrupts on address bytes. the first data byte of each frame is still accompanied by a newfrm assertion. external driver enable the uart provides a driver enable (de) si gnal for off-chip bus transceivers. this fea- ture reduces the software overhead associated with using a gpio pin to control the trans- ceiver when communicatin g on a multi-transceiver bus, such as rs-485. driver enable is an active high signal that envelopes the entire transmitted data frame including parity and stop bits as illustrated in figure 15. the driver enable signal asserts when a byte is written to the uart transmit data register. the driver enable signal asserts at least one uart bit period and no greater than two uart bit periods before the start bit is transmitted. this allows a setup time to enable the transceiver. the driver enable signal deasserts one system clock period after the last stop bit is transmitted. this one system clock delay allows both time for da ta to clear the transc eiver before disabling it, as well as the ability to dete rmine if another character follo ws the current character. in
ps019707-1003 p r e l i m i n a r y uart z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 89 the event of back to back char acters (new data must be writte n to the transmit data regis- ter before the previous character is completely transmitted) the de signal is not deasserted between characters. the depol bit in the uar t control register 1 sets the polarity of the driver enable signal. the driver enable to start bit setup time is calculated as follows: uart interrupts the uart features separate interrupts for the transmitter and the rece iver. in addition, when the uart primary functionality is disable d, the baud rate generator can also func- tion as a basic timer with interrupt capability. transmitter interrupts the transmitter generates a single interrupt when the transmit data register empty bit ( tdre ) is set to 1. this indicates that the tran smitter is ready to acce pt new data for trans- mission. the tdre interrupt occurs after the transmit shift register has shifted the first bit of data out. at this point, the transmit data register may be written with the next char- acter to send. this provides 7 bit periods of latency to load the transmit data register before the transmit shift register completes shifting the current character. writing to the uart transmit data register clears the tdre bit to 0. receiver interrupts the receiver generates an interrupt when any of the following occurs: figure 15. uart driver enable signal timing (shown with 1 stop bit and parity) start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity data field lsb msb idle state of line stop bit 1 1 0 0 1 de 1 baud rate (hz) ------------------- ------------------ ?? ?? de to start bit setup time (s) 2 baud rate (hz) ------------------- ------------------ ?? ?? ?
ps019707-1003 p r e l i m i n a r y uart z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 90 ? a data byte has been received and is av ailable in the uart receive data register. this interrupt can be disabled independent of the other receiver interrupt sources. the received data interrupt occu rs once the receive character has been received and placed in the receive data register. software must respond to this re ceived data available condition before the next character is comple tely received to avoid an overrun error. note that in multiprocessor mode ( mpen = 1), the receive data interrupts are dependent on the multiprocessor configuration and the most recent address byte. ? a break is received ? an overrun is detected ? a data framing error is detected uart overrun errors when an overrun error conditio n occurs the uart prevents overwriting of the valid data currently in the receive data register. the br eak detect and overrun status bits are not displayed until after the va lid data has been read. after the valid data has been read, the uart st atus 0 register is updated to indicate the overrun condition (and break detect, if applicable). the rda bit is set to 1 to indicate that the receive data register contains a data byte. however, because the overrun error occurred, this byte may not contain va lid data and should be ignored. the brkd bit indi- cates if the overrun was caused by a break condition on the line. after reading the status byte indicating an overrun error, the receive data register must be read again to clear the error bits is the uart status 0 register. upda tes to the receive data register occur only when the next data word is received.
ps019707-1003 p r e l i m i n a r y uart z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 91 uart data and error handling procedure figure 16 illustrates the recommended procedur e for use in uart receiver interrupt ser- vice routines. baud rate generator interrupts if the baud rate generator (brg) interrupt en able is set, the uart receiver interrupt asserts when the uart baud rate generator re loads. this action a llows the baud rate generator to function as an ad ditional counter if the uart functionality is not employed. uart baud rate generator the uart baud rate generator creates a lowe r frequency baud rate clock for data trans- mission. the input to the baud rate generator is the system clock. the uart baud rate figure 16. uart receiver int errupt service routine flow receiver errors? no yes read status discard data read data which interrupt receiver ready clears rda bit and resets error bits read data
ps019707-1003 p r e l i m i n a r y uart z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 92 high and low byte registers combine to cr eate a 16-bit baud rate divisor value (brg[15:0]) that sets the data transmission rate (baud rate) of the uart. the uart data rate is calculated usin g the following equation: when the uart is disabled, the baud rate ge nerator can function as a basic 16-bit timer with interrupt on time-out. to configure the ba ud rate generator as a timer with interrupt on time-out, complete the following procedure: 1. disable the uart by clearing the ren and ten bits in the uart control 0 register to 0. 2. load the desired 16-bit co unt value into the uart baud rate high and low byte registers. 3. enable the baud rate generator timer fu nction and associated interrupt by setting the birq bit in the uart control 1 register to 1. uart control register definitions the uart control registers support the uart and the associated infrared encoder/ decoders. for more info rmation on the infrared op eration, refer to the infrared encoder/ decoder chapter on page 102. uart transmit data register data bytes written to the uart transmit data register (table 50) are shifted out on the txd x pin. the write-only uart transmit data register shares a register file address with the read-only uart receive data register. txd?transmit data uart transmitter data byte to be shifted out through the txd x pin. table 50. uart transmit data register (u0txd) bits 7 6 5 4 3 2 1 0 field txd reset xxxxxxxx r/w wwwwwwww addr f40h uart data rate (bits/s) system clock frequency (hz) 16 uart baud rate divisor value -------------------- --------------------- ---------------------- ----------------- -------------- =
ps019707-1003 p r e l i m i n a r y uart z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 93 uart receive data register data bytes received through the rxd x pin are stored in the uart receive data register (table 51). the read-only uart receive data register shares a register file address with the write-only uart transmit data register. rxd?receive data uart receiver data byte from the rxd x pin uart status 0 register the uart status 0 and status 1 registers (table 52 and 53) identify the current uart operating configuration and status. rda?receive data available this bit indicates that the uart receive data register has received data. reading the uart receive data register clears this bit. 0 = the uart receive data register is empty. 1 = there is a byte in the uart receive data register. pe?parity error this bit indicates that a parity error has occurred. reading the uart receive data regis- ter clears this bit. table 51. uart receive data register (u0rxd) bits 7 6 5 4 3 2 1 0 field rxd reset xxxxxxxx r/w rrrrrrrr addr f40h table 52. uart status 0 register (u0stat0) bits 7 6 5 4 3 2 1 0 field rda pe oe fe brkd tdre txe cts reset 000001 1x r/w rrrrrr r r addr f41h
ps019707-1003 p r e l i m i n a r y uart z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 94 0 = no parity error has occurred. 1 = a parity error has occurred. oe?overrun error this bit indicates that an overrun error has o ccurred. an overrun occurs when new data is received and the uart receive data register has not been read. if the rda bit is reset to 0, then reading the uart receive da ta register clears this bit. 0 = no overrun error occurred. 1 = an overrun error occurred. fe?framing error this bit indicates that a framing error (no st op bit following data reception) was detected. reading the uart receive data register clears this bit. 0 = no framing error occurred. 1 = a framing error occurred. brkd?break detect this bit indicates that a break occurred. if the data bits, parity/multip rocessor bit, and stop bit(s) are all zeros then this bit is set to 1. reading the uart receive data register clears this bit. 0 = no break occurred. 1 = a break occurred. tdre?transmitter data register empty this bit indicates that the uart transmit data register is empty and ready for additional data. writing to the uart transmit data register resets this bit. 0 = do not write to the uart transmit data register. 1 = the uart transmit data register is ready to receive an additional byte to be transmit- ted. txe?transmitter empty this bit indicates that the transmit shift regist er is empty and character transmission is fin- ished. 0 = data is currently transmitting. 1 = transmission is complete.
ps019707-1003 p r e l i m i n a r y uart z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 95 cts?cts signal when this bit is read it re turns the level of the cts signal. reserved?must be 0. newfrm?status bit denoting the start of a new frame. reading the uart receive data register resets this bit to 0. 0 = the current byte is not the first data byte of a new frame. 1 = the current byte is the fi rst data byte of a new frame. mprx?multiprocessor receive returns the value of the last multiprocessor bit received. re ading from the uart receive data register resets this bit to 0. uart control 0 and c ontrol 1 registers the uart control 0 and control 1 registers (tables 54 and 55) configure the properties of the uart?s transmit and receive operatio ns. the uart control registers must not been written while the uart is enabled. uart status 1 register this register contains multipro cessor control and status bits. table 53. uart status 1 register (u0stat1) bits 7 6 5 4 3 2 1 0 field reserved newfrm mprx reset 000000 0 0 r/w rrrrr/wr/wr r addr f44h table 54. uart control 0 register (u0ctl0) bits 7 6 5 4 3 2 1 0 field ten ren ctse pen psel sbrk stop lben reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr f42h
ps019707-1003 p r e l i m i n a r y uart z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 96 ten?transmit enable this bit enables or di sables the transmitter. the enable is also controlled by the cts signal and the ctse bit. if the cts signal is low and the ctse bit is 1, the transmitter is enabled. 0 = transmitter disabled. 1 = transmitter enabled. ren?receive enable this bit enables or disables the receiver. 0 = receiver disabled. 1 = receiver enabled. ctse?cts enable 0 = the cts signal has no effect on the transmitter. 1 = the uart recognizes the cts signal as an enable control from the transmitter. pen?parity enable this bit enables or disables parity. even or odd is determined by the psel bit. 0 = parity is disabled. 1 = the transmitter sends data with an additio nal parity bit and the receiver receives an additional parity bit. psel?parity select 0 = even parity is transmitted an d expected on all received data. 1 = odd parity is transmitted an d expected on all received data. sbrk?send break this bit pauses or breaks data transmission. sending a break interrupts any transmission in progress, so ensure that the transmitter has finished sending da ta before setting this bit. 0 = no break is sent. 1 = the output of the transmitter is zero. stop?stop bit select 0 = the transmitter sends one stop bit. 1 = the transmitter sends two stop bits.
ps019707-1003 p r e l i m i n a r y uart z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 97 lben?loop back enable 0 = normal operation. 1 = all transmitted data is looped back to the receiver. mpmd[1:0]?multiprocessor mode if multiprocessor (9-bit) mode is enabled, 00 = the uart generates an interrupt requ est on all received bytes (data and address). 01 = the uart generates an interrupt request only on received address bytes. 10 = the uart generates an interrupt reques t when a received address byte matches the value stored in the address compare registr and on all successive data bytes until an address mismatch occurs. 11 = the uart generates an interrupt reques on all received data bytes for which the most recent address byte matched the value in the address compare register. mpen?multiprocesso r (9-bit) enable this bit is used to enable multiprocessor (9-bit) mode. 0 = disable multiprocessor (9-bit) mode. 1 = enable multiproces sor (9-bit) mode. mpbt?multiprocessor bit transmit this bit is applicable only when mu ltiprocessor (9-bit) mode is enabled. 0 = send a 0 in the multipro cessor bit location of the data stream (9th bit). 1 = send a 1 in the multipro cessor bit location of the data stream (9th bit). depol?driver enable polarity 0 = de signal is active high. 1 = de signal is active low. brgctl?baud rate control this bit causes different uart behavior de pending on whether the uart receiver is enabled (ren = 1 in the uart control 0 register). when the uart receiver is not enabled, this bit determines whether the baud rate gener- ator will issue interrupts. 0 = reads from the baud rate high and low byte registers return the brg reload value 1 = the baud rate generator generates a receive interrupt when it counts down to zero. table 55. uart control 1 register (u0ctl1) bits 7 6 5 4 3 2 1 0 field mpmd[1] mpen mpmd[0] mpbt depol brgctl rdairq iren reset 000000 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr f43h
ps019707-1003 p r e l i m i n a r y uart z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 98 reads from the baud rate high and low byte registers return the current brg count value. when the uart receiver is enab led, this bit allows reads from the baud rate registers to return the brg count value in stead of the reload value. 0 = reads from the baud rate high and low byte registers return the brg reload value. 1 = reads from the baud rate high and low by te registers return the current brg count value. unlike the timers, there is no mechan ism to latch the high byte when the low byte is read. rdairq ?receive data interrupt enable 0 = received data and receiver errors generat es an interrupt request to the interrupt con- troller. 1 = received data does not generate an interrupt request to the interrupt controller. only receiver errors generate an interrupt request. iren?infrared encoder/decoder enable 0 = infrared encoder/decoder is disabled . uart operates normally operation. 1 = infrared encoder/decoder is enabled. the uart transmits and r eceives data through the infrared en coder/decoder. uart address compare register the uart address compare register stores th e multi-node network address of the uart. when the mpmd[1] bit of uart control regi ster 0 is set, all incoming address bytes will be compared to the value stored in th e address compare register. receive interrupts and rda assertions will only occur in the event of a match. comp_addr?compare address this 8-bit value is co mpared to the any incoming address bytes. table 56. uart address compare register (u0addr) bits 7 6 5 4 3 2 1 0 field comp_addr reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr f45h
ps019707-1003 p r e l i m i n a r y uart z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 99 uart baud rate high and low byte registers the uart baud rate high and low byte registers (tables 57 and 57) combine to create a 16-bit baud rate divisor value (brg[15:0]) that sets the data tr ansmission rate (baud rate) of the uart. the uart data rate is calcula ted using the following equation: for a given uart data rate, the integer baud ra te divisor value is calculated using the fol- lowing equation: table 57. uart baud rate high byte register (u0brh) bits 7 6 5 4 3 2 1 0 field brh reset 11111111 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr f46h table 58. uart baud rate low byte register (u0brl) bits 7 6 5 4 3 2 1 0 field brl reset 11111111 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr f47h uart baud rate (bits/s) system clock frequency (hz) 16 uart baud rate divisor value ------------------- --------------------- --------------------- ------------------ --------------- = uart baud rate divisor value (brg) round system clock frequency (hz) 16 uart data rate (bits/s) ------------------- --------------------- ---------------------- -------------- ?? ?? =
ps019707-1003 p r e l i m i n a r y uart z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 100 the baud rate error relative to the desired baud rate is calcu lated using the following equa- tion: for reliable communication, the uart baud ra te error must never exceed 5 percent. table 59 provides information on data rate e rrors for popular baud rates and commonly used crystal osc illator frequencies. table 59. uart baud rates 10.0 mhz system clock 5.5296 mhz system clock desired rate brg divisor actual rate error d esired rate brg divisor actual rate error (khz) (decimal) (khz) (%) (khz) (decimal) (khz) (%) 1250.0 n/a n/a n/a 1250.0 n/a n/a n/a 625.0 1 625.0 0.00 625.0 n/a n/a n/a 250.0 3 208.33 -16.67 250.0 1 345.6 38.24 115.2 5 125.0 8.51 115.2 3 115.2 0.00 57.6 11 56.8 -1.36 57.6 6 57.6 0.00 38.4 16 39.1 1.73 38.4 9 38.4 0.00 19.2 33 18.9 0.16 19.2 18 19.2 0.00 9.60 65 9.62 0.16 9.60 36 9.60 0.00 4.80 130 4.81 0.16 4.80 72 4.80 0.00 2.40 260 2.40 -0.03 2.40 144 2.40 0.00 1.20 521 1.20 -0.03 1.20 288 1.20 0.00 0.60 1042 0.60 -0.03 0.60 576 0.60 0.00 0.30 2083 0.30 0.2 0.30 1152 0.30 0.00 3.579545 mhz system clock 1.8432 mhz system clock desired rate brg divisor actual rate error d esired rate brg divisor actual rate error (khz) (decimal) (khz) (%) (khz) (decimal) (khz) (%) 1250.0 n/a n/a n/a 1250.0 n/a n/a n/a 625.0 n/a n/a n/a 625.0 n/a n/a n/a 250.0 1 223.72 -10.51 250.0 n/a n/a n/a uart baud rate error (%) 100 actual data rate desired data rate ? desired data rate ------------------- --------------------- --------------------- ------------------ ----------------- - ?? ?? =
ps019707-1003 p r e l i m i n a r y z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 101 115.2 2 111.9 -2.90 115.2 1 115.2 0.00 57.6 4 55.9 -2.90 57.6 2 57.6 0.00 38.4 6 37.3 -2.90 38.4 3 38.4 0.00 19.2 12 18.6 -2.90 19.2 6 19.2 0.00 9.60 23 9.73 1.32 9.60 12 9.60 0.00 4.80 47 4.76 -0.83 4.80 24 4.80 0.00 2.40 93 2.41 0.23 2.40 48 2.40 0.00 1.20 186 1.20 0.23 1.20 96 1.20 0.00 0.60 373 0.60 -0.04 0.60 192 0.60 0.00 0.30 746 0.30 -0.04 0.30 384 0.30 0.00 table 59. uart baud rates (continued)
z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? ps019707-1003 p r e l i m i n a r y infrared encoder/decoder 102 infrared encoder/decoder overview the z8f082x family products contain a fu lly-functional, high-performance uart to infrared encoder/decoder (endec ). the infrared endec is in tegrated with an on-chip uart to allow easy communicat ion between the z8 encore! ? and irda physical layer specification, version 1.3-compliant infrare d transceivers. infrared communication pro- vides secure, reliable, low-co st, point-to-point communica tion between pcs, pdas, cell phones, printers and other infrared enabled devices. architecture figure 17 illustrates the archite cture of the infrared endec. figure 17. infrared data communi cation system block diagram interrupt signal rxd txd infrared encoder/decoder uart rxd txd system clock i/o address data zilog rxd txd baud rate clock (endec) zhx1810 infrared transceiver
ps019707-1003 p r e l i m i n a r y infrared encoder/decoder z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 103 operation when the infrared endec is en abled, the transmit data from the associated on-chip uart is encoded as digital signals in accordance with the irda standard and output to the infra- red transceiver via the txd pin. likewise, da ta received from the in frared transceiver is passed to the infrared endec via the rxd pin, decoded by the infrared endec, and then passed to the uart. communication is hal f-duplex, which means simultaneous data transmission and reception is not allowed. the baud rate is set by the uart?s baud rate generator and supports irda standard baud rates from 9600 baud to 115.2 kbaud. higher baud rates are possible, but do not meet irda specifications. the uart must be enable d to use the infrared endec. the infrared endec data rate is calculated using the following equation: transmitting irda data the data to be transmitted using the infrared transceiver is first se nt to the uart. the uart?s transmit signal (txd) and baud rate clock are used by the irda to generate the modulation signal (ir_txd) that drives th e infrared transceiver. each uart/infrared data bit is 16-clocks wide. if the data to be transmitted is 1, the ir_txd signal remains low for the full 16-clock period. if the data to be transmi tted is 0, a 3-clock high pulse is output following a 7-clock low period. after the 3-clock high pulse, a 6-clock low pulse is output to complete the full 16 -clock data period. figure 18 illustrates irda data transmis- sion. when the infrared endec is enabled, the uart?s txd signal is internal to the z8f082x family products while the ir_t xd signal is output through the txd pin. infrared data rate (bits/s) system clock frequency (hz) 16 uart baud rate divisor value --------------------- --------------------- ------------------ ------------------ ---------------- =
ps019707-1003 p r e l i m i n a r y infrared encoder/decoder z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 104 figure 18. infrared data transmission receiving irda data data received from the infrared transceiver via the ir_rxd signal through the rxd pin is decoded by the infrared endec and passed to the uart. the uart?s baud rate clock is used by the infrared endec to generate th e demodulated signal (rxd) that drives the uart. each uart/infrared data bit is 16-c locks wide. figure 19 illustrates data recep- tion. when the infrared endec is enabled, the uart?s rxd signal is internal to the z8f082x family products while the ir_rxd signal is received through the rxd pin. baud rate ir_txd uart?s 16-clock period start bit = 0 data bit 0 = 1 data bit 1 = 0 data bit 2 = 1 data bit 3 = 1 7-clock delay 3-clock pulse txd clock
ps019707-1003 p r e l i m i n a r y infrared encoder/decoder z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 105 figure 19. infrared data reception the system clock frequency must be at least 1.0mhz to ensure proper re- ception of the 1.6 s minimum width pulses allowed by the irda standard. endec receiver synchronization the irda receiver uses a local baud rate clock co unter (0 to 15 clock periods) to generate an input stream for the uart and to create a sampling window for detection of incoming pulses. the generated uart input (uart rxd) is delayed by 8 baud rate clock periods with respect to the incoming irda data stream. when a fa lling edge in the input data stream is detected, the endec counter is rese t. when the count reac hes a value of 8, the uart rxd value is updated to reflect the va lue of the decoded data. when the count reaches 12 baud clock periods, the sampling window for the next incoming pulse opens. the window remains open until the count again reaches 8 (or in other words 24 baud clock periods since the previous pulse was detected ). this gives the endec a sampling window of minus four baudrate clocks to plus eight baudrate clocks around the expected time of an incoming pulse. if an incoming pulse is dete cted inside this window this process is repeated. if the incoming data is a logical 1 (n o pulse), the endec returns to the initial state and waits for the next falling edge. as eac h falling edge is detected, the endec clock counter is reset, resynchronizing the endec to the incoming signal. this allows the endec to tolerate jitter and baud rate errors in th e incoming data stream. resynchronizing the endec does not alter the opera tion of the uart, which ultima tely receives the data. the uart is only synchronized to the incoming data stream when a start bit is received. baud rate uart?s ir_rxd 16-clock period start bit = 0 data bit 0 = 1 data bit 1 = 0 data bit 2 = 1 data bit 3 = 1 8-clock delay clock rxd 16-clock period 16-clock period 16-clock period 16-clock period start bit = 0 data bit 0 = 1 data bit 1 = 0 data bit 2 = 1 data bit 3 = 1 min. 1.6 s pulse caution:
ps019707-1003 p r e l i m i n a r y infrared encoder/decoder z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 106 infrared encoder/decoder co ntrol register definitions all infrared endec configuration and status information is set by the uart control regis- ters as defined beginning on page 92 . to prevent spurious signals during irda data transmission, set the iren bit in the uart control 1 register to 1 to enable the infrared encoder/de- coder before enabling the gpio port altern ate function for the correspond- ing pin. caution:
z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? ps019707-1003 p r e l i m i n a r y serial peripheral interface 107 serial peripheral interface overview the serial peripheral interface tm (spi) is a synchronous inte rface allowing several spi- type devices to be interconnected. spi-com patible devices include eeproms, analog-to- digital converters, and isdn devices. features of the spi include: ? full-duplex, synchronous, character-oriented communication ? four-wire interface ? data transfers rates up to a maximum of one-half the system clock frequency ? error detection ? dedicated baud rate generator the spi is unavailable in 20-pin package devices. architecture the spi may be configured as either a master (in single or multi-master systems) or a slave as illustrated in figures 20 through 22. figure 20. spi configured as a master in a single master, single slave system spi master 8-bit shift register bit 7 bit 0 miso mosi sck ss to slave?s ss pin from slave to slave to slave baud rate generator
ps019707-1003 p r e l i m i n a r y serial peripheral interface z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 108 figure 21. spi configured as a master in a single master, multiple slave system figure 22. spi configured as a slave operation the spi is a full-duplex, synchronous, characte r-oriented channel that supports a four-wire interface (serial clock, transmit, receive an d slave select). the spi block consists of a transmit/receive shift regist er, a baud rate (clock) ge nerator and a control unit. spi master 8-bit shift register bit 7 bit 0 miso mosi sck gpio to slave #2?s ss pin from slave to slave to slave ss baud rate generator vcc gpio to slave #1?s ss pin spi slave 8-bit shift register bit 7 bit 0 miso mosi sck ss from master to master from master from master
ps019707-1003 p r e l i m i n a r y serial peripheral interface z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 109 during an spi transfer, data is sent and recei ved simultaneously by both the master and the slave spi devices. separate signals are requ ired for data and the serial clock. when an spi transfer occurs, a multi-bit (typically 8-bit) character is shifted out one data pin and an multi-bit character is simultaneou sly shifted in on a second data pin. an 8-bit shift register in the master and another 8-bit shift register in the slave are connected as a circular buffer. the spi shift register is single-buffered in th e transmit and receive directions. new data to be transmitted cannot be written into the shift register until the previous transmission is complete and receive data (if valid) has been read. spi signals the four basic spi signals are: ? miso (master-in, slave-out) ? mosi (master-out, slave-in) ? sck (serial clock) ? ss (slave select) the following paragraphs discuss these spi signal s. each signal is de scribed in both mas- ter and slave modes. master-in, slave-out the master-in, slave-out (miso) pin is config ured as an input in a master device and as an output in a slave device. it is one of the tw o lines that transfer serial data, with the most significant bit sent first. the miso pin of a slave device is placed in a high-impedance state if the slave is not selected. when the sp i is not enabled, this signal is in a high- impedance state. master-out, slave-in the master-out, slave-in (mosi) pin is configur ed as an output in a master device and as an input in a slave device. it is one of the tw o lines that transfer serial data, with the most significant bit sent first. when the spi is not enabled, this signal is in a high-impedance state. serial clock the serial clock (sck) synchronizes data movement both in and out of the device through its mosi and miso pins. in master mode, the spi?s baud rate generator cre- ates the serial clock. the master drives the serial clock out its own sck pin to the slave?s sck pin. when the spi is configured as a slav e, the sck pin is an input and the clock sig- nal from the master synchronizes the data tran sfer between the master and slave devices. slave devices ignore the sck signal, unless the ss pin is asserted. when configured as a slave, the spi block requires a minimum sck pe riod of greater than or equal to 8 times the system (xin) clock period.
ps019707-1003 p r e l i m i n a r y serial peripheral interface z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 110 the master and slave are each capable of exchanging a character of data during a sequence of numbits clock cycles (refer to numbits field in the spimode register). in both master and slave spi devices, data is shifted on one edge of the sck and is sam- pled on the opposite edge where data is stab le. edge polarity is determined by the spi phase and polarity control. slave select the active low slave select (ss ) input signal selects a slave spi device. ss must be low prior to all data communication to and from the slave device. ss must stay low for the full duration of each character transferred. the ss signal may stay low during the transfer of multiple characters or may deassert between each character. when the spi is configured as the only master in an spi system, the ss pin can be set as either an input or an output. for communic ation between the z8f082x family device?s spi master and external slave devices, the ss signal, as an output, can assert the ss input pin on one of the slave devices. other gpio outp ut pins can also be employed to select exter- nal spi slave devices. when the spi is configured as one master in a multi-master spi system, the ss pin should be set as an input. the ss input signal on the master must be high. if the ss signal goes low (indicating another master is driving the spi bus), a collision error flag is set in the spi status register. spi clock phase and polarity control the spi supports four combinations of serial cl ock phase and polarity using two bits in the spi control register. the clock polarity bit, clkpol , selects an active high or active low clock and has no effect on the transfer format. table 60 lists the spi clock phase and polarity operation parameters. the clock phase bit, phase , selects one of two fundamen- tally different transfer formats. for proper da ta transmission, the clock phase and polarity must be identical for the spi master and the spi slave. the master always places data on the mosi line a half-cycle befo re the receive clock edge (sck signal), in order for the slave to latch the data. table 60. spi clock phase ( phase ) and clock polarity ( clkpol ) operation phase clkpol sck transmit edge sck receive edge sck idle state 0 0 falling rising low 0 1 rising falling high 1 0 rising falling low 1 1 falling rising high
ps019707-1003 p r e l i m i n a r y serial peripheral interface z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 111 transfer format phase equals zero figure 23 illustrates the timing diag ram for an spi transfer in which phase is cleared to 0. the two sck waveforms show polarity with clkpol reset to 0 and with clkpol set to one. the diagram may be interpreted as either a master or slave timing diagram since the sck master-in/slave-out (m iso) and master-out/slave-in (mosi) pins are directly connected between the master and the slave. figure 23. spi timing when phase is 0 transfer format phase equals one figure 24 illustrates the timin g diagram for an spi transfer in which phase is one. two waveforms are depicted for sck, one for cl kpol reset to 0 and another for clkpol set to 1. sck (clkpol = 0) sck (clkpol = 1) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 mosi bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 miso input sample time ss
ps019707-1003 p r e l i m i n a r y serial peripheral interface z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 112 figure 24. spi timing when phase is 1 multi-master operation in a multi-master spi system, all sck pins are tied together, all mosi pins are tied together and all miso pins are tied together. all spi pins must then be configured in open-drain mode to prevent bus contention . at any one time, only one spi device is configured as the master and all other spi de vices on the bus are configured as slaves. the master enables a single slave by asserting the ss pin on that slave only. then, the single master drives data out its sck and mo si pins to the sck and mosi pins on the slaves (including those which are not enable d). the enabled slave drives data out its miso pin to the miso master pin. for a master device operating in a multi-master system, if the ss pin is configured as an input and is driven low by another master, the col bit is set to 1 in the spi status regis- ter. the col bit indicates the occurrence of a multi- master collision (mode fault error con- dition). slave operation the spi block is configured for slave mode operation by setting the spien bit to 1 and the mmen bit to 0 in the spi ctl register and setting the ssi o bit to 0 in the spimode sck (clkpol = 0) sck (clkpol = 1) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 mosi bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 miso input sample time ss
ps019707-1003 p r e l i m i n a r y serial peripheral interface z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 113 register. the irqe, phase, clkpol, wor bits in the spictl register and the num- bits field in the spimode register must be set to be consistent with the other spi devices. the str bit in the spictl register may be used if desired to force a ?startup? interrupt. the birq bit in the spictl register and the ssv bit in the spimode register are not used in slave mode. the spi baud rate generator is not used in slave mode so the spibrh and spibrl registers need not be initialized. if the slave has data to send to the master, the data should be written to the spidat regis- ter before the transaction starts (first edge of sck when ss is asserted). if the spidat register is not written prior to the slave tran saction, the miso pin outputs whatever value is currently in the spidat register. due to the delay resulting from s ynchronization of the spi input signals to the internal sys- tem clock, the maximum spiclk baud rate th at can be supported in slave mode is the system clock frequency (xin) divided by 8. this rate is controlled by the spi master. error detection the spi contains error detection logic to support spi communication protocols and recog- nize when communication errors have occurred. the spi status register indicates when a data transmission error has been detected. overrun (write collision) an overrun error (write collisi on) indicates a write to the spi data register was attempted while a data transfer is in pr ogress (in either master or slave modes). an overrun sets the ovr bit in the spi status register to 1. writin g a 1 to ovr clears this error flag . the data register is not altered when a write occu rs while data transfer is in progress. mode fault (multi-master collision) a mode fault indicates when mo re than one master is trying to communicate at the same time (a multi-master collision). the mode fault is detected when the enabled master?s ss pin is asserted. a mode fault sets the col bit in the spi status register to 1. writing a 1 to col clears this error flag. slave mode abort in slave mode, if the ss pin deasserts before all bits in a character have been trans- ferred, the transaction aborts. wh en this condition occurs the abt bit is set in the spistat register as well as the irq bit (indicating the transaction is complete). the next time ss asserts, the miso pin outputs spidat[7], rega rdless of where the previous transaction left off. writing a 1 to abt clears this error flag. spi interrupts when spi interrupts are enabled, the spi gene rates an interrupt after character transmis- sion/reception completes in both master and slave modes. a ch aracter can be defined to be
ps019707-1003 p r e l i m i n a r y serial peripheral interface z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 114 1 through 8 bits by the numbits field in the spi mode register. in slave mode it is not necessary for ss to deassert between characters to generate the interrupt. the spi in slave mode can also generate an interrupt if the ss signal deasserts prior to transfer of all the bits in a character (see description of slave abort error above). writing a 1 to the irq bit in the spi status register clears the pending spi interrupt request. the irq bit must be cleared to 0 by the interrupt service ro utine to generate future interrupts. to start the transfer process, an spi interrupt may be forced by software writing a 1 to the str bit in the spictl register. if the spi is disabled, an spi interrupt can be generated by a baud rate generator time- out. this timer function must be enabled by setting the birq bit in the spictl register. this baud rate generator time- out does not set the irq bit in the spistat register, just the spi interrupt bit in the interrupt controller. spi baud rate generator in spi master mode, the baud rate generato r creates a lower frequency serial clock (sck) for data transmission synchronization between the master and the external slave. the input to the baud rate ge nerator is the system clock. the spi baud rate high and low byte registers combine to form a 16-bit reload value, brg[15:0], for the spi baud rate generator. the spi baud rate is calculated using the following equation: minimum baud rate is obtained by setting brg [15:0] to 0000h for a clock divisor value of (2 x 65536 = 131072). when the spi is disabled, the baud rate generator can function as a basic 16-bit timer with interrupt on time-out. to configure the ba ud rate generator as a timer with interrupt on time-out, complete the following procedure: 1. disable the spi by clearing the spien bit in the spi control register to 0. 2. load the desired 16-bit co unt value into the spi baud rate high and low byte registers. 3. enable the baud rate generator timer fu nction and associated interrupt by setting the birq bit in the spi control register to 1. spi control register definitions spi data register the spi data register stores both the outgoing (transmit) data and the incoming (receive) data. reads from the spi data register always re turn the current contents of the 8-bit shift spi baud rate (bits/s) system clock frequency (hz) 2 brg[15:0] ------------------- ---------------------- --------------------- -------------- =
ps019707-1003 p r e l i m i n a r y serial peripheral interface z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 115 register. data is shifted out starting with bit 7. the last bit received resides in bit position 0. with the spi configured as a master, writing a da ta byte to this register initiates the data transmission. with the spi conf igured as a slave, writing a data byte to this register loads the shift register in preparation for the next data transfer with the external master. in either the master or slave modes, if a transmission is already in progress, writes to this register are ignored and the overrun error flag, ovr , is set in the spi status register. when the character length is le ss than 8 bits (as set by the numbits field in the spi mode register), the transmit character must be left justified in the spi data register. a received character of less than 8 bits is right justifie d (last bit received is in bit position 0). for example, if the spi is configured for 4-bit ch aracters, the transmit characters must be writ- ten to spidata[7:4] and the received characters are read from spidata[3:0]. data?data transmit and/or receive data. spi control register the spi control register configures the spi for transmit and receive operations. table 61. spi data register (spidata) bits 7 6 5 4 3 2 1 0 field data reset xxxxxxxx r/w r/w r/w r/w r/w r/w r/w r/w r/w addr f60h table 62. spi control register (spictl) bits 7 6 5 4 3 2 1 0 field irqe str birq phase clkpol wor mmen spien reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr f61h
ps019707-1003 p r e l i m i n a r y serial peripheral interface z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 116 irqe?interrupt request enable 0 = spi interrupts are disabled. no interrupt requests are sent to the interrupt controller. 1 = spi interrupts are enabled. interrupt re quests are sent to the interrupt controller. str?start an spi interrupt request 0 = no effect. 1 = setting this bit to 1 also sets the irq bit in the spi status register to 1. setting this bit forces the spi to send an interrupt request to the interrupt contro l. this bit can be used by software for a function similar to transmit buffer empty in a uart. writing a 1 to the irq bit in the spi status register clears this bit to 0. birq?brg timer interrupt request if the spi is enabled, this bit h as no effect. if the spi is disabled: 0 = the baud rate generator timer function is disabled. 1 = the baud rate generator timer func tion and time-out interrupt are enabled. phase?phase select sets the phase relationship of the data to th e clock. refer to the spi clock phase and polarity control section for more information on op eration of the phase bit. clkpol?clock polarity 0 = sck idles low (0). 1 = sck idle high (1). wor?wire-or (open-drain) mode enabled 0 = spi signal pins not configured for open-drain. 1 = all four spi signal pins (sck, ss , miso, mosi) configured for open-drain function. this setting is typically used for multi- master and/or multi-sl ave configurations. mmen?spi master mode enable 0 = spi configured in slave mode. 1 = spi configured in master mode. spien?spi enable 0 = spi disabled. 1 = spi enabled. spi status register the spi status register indicates the current stat e of the spi. all bits revert to their reset state if the spien bit in the spictl register = 0.
ps019707-1003 p r e l i m i n a r y serial peripheral interface z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 117 irq?interrupt request if spien = 1, this bit is set if the str bit in the spictl register is set, or upon completion of an spi master or slave tr ansaction. this bit does not set if spien = 0 and the spi baud rate generator is used as a timer to generate the spi interrupt. 0 = no spi interrupt request pending. 1 = spi interrupt request is pending. ovr?overrun 0 = an overrun error has not occurred. 1 = an overrun error has been detected. col?collision 0 = a multi-master collision (m ode fault) has not occurred. 1 = a multi-master collision (mod e fault) has been detected. abt?slave mode transaction abort this bit is set if the spi is configured in slave mode, a transaction is occurring and ss deasserts before all bits of a character have been transferred as defined by the numbits field of the spimode register. the irq bit al so sets, indicating the transaction has com- pleted. 0 = a slave mode transaction abort has not occurred. 1 = a slave mode transaction abort has been detected. reserved?must be 0. txst?transmit status 0 = no data transmission currently in progress. 1 = data transmission cu rrently in progress. slas?slave select if spi enabled as a slave, 0 = ss input pin is asserted (low) 1 = ss input is not asserted (high). if spi enabled as a master, th is bit is not applicable. table 63. spi status register (spistat) bits 7 6 5 4 3 2 1 0 field irq ovr col abt reserved txst slas reset 0000 0 0 1 r/w r/w* r/w* r/w* r/w* r rr addr f62h r/w* = read access. write a 1 to clear the bit to 0.
ps019707-1003 p r e l i m i n a r y serial peripheral interface z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 118 spi mode register the spi mode register configures the character bit width and the direction and value of the ss pin. reserved?must be 0. diag - diagnostic mode control bit this bit is for spi diagnostics. setting this bi t allows the baud rate generator value to be read using the spibrh and spibrl register locations. 0 = reading spibrh, spibrl returns the valu e in the spibrh and spibrl registers 1 = reading spibrh returns bits [15:8] of th e spi baud rate genera tor; and reading spi- brl returns bits [7:0] of the spi baud rate counter. the baud rate counter high and low byte values are not buffered. exercise caution if reading the va lues while the brg is counting. numbits[2:0]?number of data b its per character to transfer this field contains the number of bits to shift for each char acter transfer. refer to the spi data register description for information on valid bit positio ns when the character length is less than 8-bits. 000 = 8 bits 001 = 1 bit 010 = 2 bits 011 = 3 bits 100 = 4 bits 101 = 5 bits 110 = 6 bits 111 = 7 bits. ssio?slave select i/o 0 = ss pin configured as an input. 1 = ss pin configured as an output (master mode only). table 64. spi mode register (spimode) bits 7 6 5 4 3 2 1 0 field reserved diag numbits[2:0] ssio ssv reset 0000000 r/w r r/w r/w r/w r/w r/w r/w addr f63h caution:
ps019707-1003 p r e l i m i n a r y serial peripheral interface z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 119 ssv?slave select value if ssio = 1 and spi configured as a master: 0 = ss pin driven low (0). 1 = ss pin driven high (1). this bit has no effect if ssio = 0 or spi configured as a slave. spi diagnostic state register the spi diagnostic state register provides obse rvability of internal state. this is a read only register used for spi diagnostics. scken - shift clock enable 0 = the internal shift clock enable signal is deasserted 1 = the internal shift clock enab le signal is asserted (shift register is updates on next sys- tem clock) tcken - transmit clock enable 0 = the internal transmit clock enable signal is deasserted. 1 = the internal transmit clock enable signal is asserted. when this is asserted the serial data out is updated on the next system clock (mosi or miso). spistate - spi state machine defines the current state of th e internal spi state machine. table 65. spi diagnostic state register (spidst) bits 7 6 5 4 3 2 1 0 field scken tcken spistate reset 00 0 r/w rr r addr f64h
ps019707-1003 p r e l i m i n a r y serial peripheral interface z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 120 spi baud rate high and low byte registers the spi baud rate high and low byte regist ers combine to form a 16-bit reload value, brg[15:0], for the spi baud rate generator. the spi baud rate is calculated using the following equation: minimum baud rate is obtained by setting brg[15:0] to 0000h for a clock divisor value of (2 x 65536 = 131072). brh = spi baud rate high byte most significant byte, brg[1 5:8], of the spi baud rate generator?s reload value. brl = spi baud rate low byte least significant byte, brg[7:0], of the spi baud rate generator?s reload value. table 66. spi baud rate high byte register (spibrh) bits 7 6 5 4 3 2 1 0 field brh reset 11111111 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr f66h table 67. spi baud rate lo w byte register (spibrl) bits 7 6 5 4 3 2 1 0 field brl reset 11111111 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr f67h spi baud rate (bits/s) system clock frequency (hz) 2 brg[15:0] ------------------- ---------------------- --------------------- -------------- =
z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? ps019707-1003 p r e l i m i n a r y i2c controller 121 i 2 c controller overview the i 2 c controller makes the z8f082x family products bus-compatible with the i 2 c tm protocol. the i 2 c controller consists of two bidirec tional bus lines?a serial data signal (sda) and a serial clock signal (scl). features of the i 2 c controller include: ? transmit and receive operation in master mode ? maximum data rate of 400kbit/sec ? 7- and 10-bit addressing modes for slaves ? unrestricted number of data bytes transmitted per transfer the i 2 c controller in the z8f082x family prod ucts does not operate in slave mode. operation the i 2 c controller operates in master mode to tr ansmit and receive data. only a single master is supported. arbitration between two masters must be accomplished in software. i 2 c supports the follo wing operations: ? master transmits to a 7-bit slave ? master transmits to a 10-bit slave ? master receives from a 7-bit slave ? master receives from a 10-bit slave sda and scl signals i 2 c sends all addresses, data and acknowledge signals over the sda line, most-significant bit first. scl is the common clock for the i 2 c controller. when the sda and scl pin alternate functions are selected for their respective gpio port s, the pins are automatically configured for open -drain operation. the master (i 2 c) is responsible for driving the scl clock signal, although the clock signal can become skewed by a slow slave device. duri ng the low period of the clock, the slave pulls the scl signal low to suspend the tran saction. the master releases the clock at the end of the low period and notices that the clock remains low instead of returning to a
ps019707-1003 p r e l i m i n a r y i2c controller z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 122 high level. when the slave h as released the clock, the i 2 c controller continues the trans- action. all data is transferred in bytes and th ere is no limit to the amount of data trans- ferred in one operation. when transmitting data or acknow ledging read data from the slave, the sda signal changes in the middle of the low period of scl and is sampled in the middle of the high period of scl. i 2 c interrupts the i 2 c controller contains four sources of in terrupts?transmit, receive, not acknowl- edge (nak) and baud rate generator. these four interrupt sources are combined into a sin- gle interrupt request signal to the interrupt controller. nak interrupts occur when a not acknowledge is received from the slave or sent by the i 2 c controller and the start or stop bit is not set. the nak event sets bit 0 of the i2cstat register and can only be cleared by setting the start or stop bit. when this interrupt occurs, the i 2 c controller waits until it is cleared before perform ing any action. in an interrupt serv ice routine, the nak interrupt must be the first item polled. receive interrupts occur when a byte of data has been r eceived by the i 2 c master. the receive interrupt is cleared by reading from the i 2 c data register. if no action is taken, the i 2 c controller waits until this interrupt is cleared before performing any other action. for transmit interrupts to occur, the txi bit must be 1 in the i 2 c control register. trans- mit interrupts occur un der the following cond itions when the transmit data register is empty: ? the i 2 c controller is enabled ? the first bit of the byte of an address is shifting out and the rd bit of the i 2 c status register is deasserted ? the first bit of a 10-bit address shifts out ? the first bit of write data shifted out writing to the i 2 c data register always clears the trde bit to 0. the fourth interrupt source is the baud rate generator. if th e i2c controller is disabled (ien bit in the i2cctl register = 0) and the birq b it in the i2cctl register = 1, an interrupt is generated when the baud rate generator counts down to 1. start and stop conditions the master (i 2 c) drives all start and stop signals an d initiates all transactions. to start a transaction, the i 2 c controller generates a start condition by pu lling the sda signal low while scl is high. to complete a transaction, the i 2 c controller generates a stop condition by creating a low-to-high transition of the sda signal while the scl signal is high. the start and stop signals are found in the i 2 c control register and must be written by software when the z8f0 82x family device must begin or end a transaction. note:
ps019707-1003 p r e l i m i n a r y i2c controller z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 123 write transaction wi th a 7-bit address figure 25 illustrates the data transfer format for a 7-bit addressed slave. shaded regions indicate data transferred from the i 2 c controller to slaves and unshaded regions indicate data transferred from the slaves to the i 2 c controller. figure 25. 7-bit addressed slave data transfer format the procedure for a transmit operation on a 7-bit addressed slave is as follows: 1. software asserts the ien bit in the i 2 c control register. 2. software asserts the txi bit of the i 2 c control register to enable transmit interrupts. 3. the i 2 c interrupt asserts, because the i 2 c data register is empty 4. software responds to the tdre bit by writing a 7-bit slave address plus write bit (=0) to the i 2 c data register. 5. software asserts the start bit of the i 2 c control register. 6. the i 2 c controller sends the start condition to the i 2 c slave. 7. the i 2 c controller loads the i 2 c shift register with the contents of the i 2 c data register. 8. after one bit of address has been shifted ou t by the sda signal, the transmit interrupt is asserted. 9. software responds by writing the transmit data into the i 2 c data register. 10. the i 2 c controller shifts the rest of the ad dress and write bit out by the sda signal. 11. the i 2 c slave sends an acknowledge (by pulling the sda signal low) during the next high period of scl. the i 2 c controller sets the ack bit in the i 2 c status register. 12. the i 2 c controller loads the contents of the i 2 c shift register with the contents of the i 2 c data register. 13. the i 2 c controller shifts the data out of via th e sda signal. after the first bit is sent, the transmit interrupt is asserted. 14. if more bytes remain to be sent, return to step 9 15. software responds by setting the stop bit of the i 2 c control register (or start bit to initiate a new transaction). 16. if no new data is to be sent or address is to be sent, software responds by clearing the txi bit of the i 2 c control register. a a data a data p/s s a/a slave address w=0 data
ps019707-1003 p r e l i m i n a r y i2c controller z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 124 17. the i 2 c controller completes transmission of the data on the sda signal. 18. the i 2 c controller sends the stop condition to the i 2 c bus. write transaction wi th a 10-bit address figure 26 illustrates the data transfer format for a 10-bit addressed slave. shaded regions indicate data transferred from the i 2 c controller to slaves and unshaded regions indicate data transferred from the slaves to the i 2 c controller. figure 26. 10-bit addressed slave data transfer format the first seven bits transmi tted in the first byte are 11110xx . the two bits xx are the two most-significant bits of the 10-bit address. the lowest bit of the first byte transferred is the read/write control bit (=0). the transmit oper ation is carried out in the same manner as 7- bit addressing. the procedure for a transmit operation on a 10-bit addressed slave is as follows: 1. software asserts the ien bit in the i 2 c control register. 2. software asserts the txi bit of the i 2 c control register to enable transmit interrupts. 3. the i 2 c interrupt asserts because the i 2 c data register is empty. 4. software responds to the tdre interrupt by writing the fi rst slave address byte. the least-significant bit must be 0 for the write operation. 5. software asserts the start bit of the i 2 c control register. 6. the i 2 c controller sends the start condition to the i 2 c slave. 7. the i 2 c controller loads the i 2 c shift register with the contents of the i 2 c data register. 8. after one bit of address is shifted out by the sda signal, the transmit interrupt is asserted. 9. software responds by writing the second byte of address in to the contents of the i 2 c data register. 10. the i 2 c controller shifts the rest of the first byte of address and write bit out the sda signal. 11. the i 2 c slave sends an acknowledge by pulling the sda signal low during the next high period of scl. the i 2 c controller sets the ack bit in the i 2 c status register. 12. the i 2 c controller loads the i 2 c shift register with the contents of the i 2 c data register. a a data a data p/s slave address 2nd byte s a/a slave address 1st 7 bits w=0
ps019707-1003 p r e l i m i n a r y i2c controller z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 125 13. the i 2 c controller shifts the second address byte out the sda signal. after the first bit has been sent, the transmit interrupt is asserted. 14. software responds by writing the da ta to be written out to the i 2 c control register. 15. the i 2 c controller shifts out the rest of the second byte of slave address by the sda signal. 16. the i 2 c slave sends an acknowledge by pulling the sda signal low during the next high period of scl. the i 2 c controller sets the ack bit in the i 2 c status register. 17. the i 2 c controller shifts the data out by the s da signal. after the first bit is sent, the transmit interrupt is asserted. 18. software responds by asserting the stop bit of the i 2 c control register. 19. the i 2 c controller completes transmission of the data on the sda signal. 20. the i 2 c controller sends the stop condition to the i 2 c bus. read transaction wi th a 7-bit address figure 27 illustrates the data transfer format fo r a read operation to a 7-bit addressed slave. the shaded regions indicate data transferred from the i 2 c controller to slaves and unshaded regions indicate data tr ansferred from the slaves to the i 2 c controller. figure 27. receive data transfer format for a 7-bit addressed slave the procedure for a read operation to a 7-bit addressed slave is as follows: 1. software writes the i 2 c data register with a 7-bit slave address plus the read bit (=1). 2. software asserts the start bit of the i 2 c control register. 3. if this is a single byte transfer, software asserts the nak bit of the i 2 c control register so that after the first byte of data has been read by the i 2 c controller, a not acknowledge is sent to the i 2 c slave. 4. the i 2 c controller sends the start condition. 5. the i 2 c controller sends the address and read bit out the sda signal. 6. the i 2 c slave acknowledges the address by pu lling the sda signal low during the next high period of scl. 7. the i 2 c controller shifts in the first byte of data from the i 2 c slave on the sda signal. 8. the i 2 c controller asserts the receive interrupt. s slave address r=1 a data a data a p/s
ps019707-1003 p r e l i m i n a r y i2c controller z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 126 9. software responds by reading the i 2 c data register. 10. the i 2 c controller sends a nak to the i 2 c slave (if this is the last byte). 11. if there are more bytes to transfer, return to step 7. 12. a nak interrupt is generated by the i 2 c controller. 13. software responds by setting the stop bit of the i 2 c control register. 14. a stop condition is sent to the i 2 c slave. read transaction wi th a 10-bit address figure 28 illustrates the read transaction form at for a 10-bit addressed slave. the shaded regions indicate data transferred from the i 2 c controller to slaves and unshaded regions indicate data transferred from the slaves to the i 2 c controller. figure 28. receive data format for a 10-bit addressed slave the first seven bits transmi tted in the first byte are 11110xx . the two bits xx are the two most-significant bits of the 10-bit address. the lowest bit of the first byte transferred is the write control bit. the data transfer procedure for a read opera tion to a 10-bit addressed slave is as follows: 1. software writes 11110b followed by the two address bits and a 0 (write) to the i2c data register. 2. software asserts the start bit of the i 2 c control register. 3. the i 2 c controller sends the start condition. 4. the i 2 c controller loads the i 2 c shift register with the contents of the i 2 c data register. 5. after the first bit has been shifted out, a transmit interrupt is asserted. 6. software responds by writing ei ght bits of address to the i 2 c data register. 7. the i 2 c controller completes shifting of th e two address bits and a 0 (write). 8. the i 2 c slave sends an acknowledge by pulling the sda signal low during the next high period of scl. 9. the i 2 c controller loads the i 2 c shift register with the contents of the i 2 c data register (lower byte of 10 bit address). a s a data p slave address 2nd byte s a slave address 1st 7 bits w=0 slave address 1st 7 bits r=1 a data a
ps019707-1003 p r e l i m i n a r y i2c controller z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 127 10. the i 2 c controller shifts out the next eight bits of address. after the first bit is shifted, the i 2 c controller generates a transmit interrupt. 11. software responds by setting the start bit of the i 2 c control register to generate a repeated start. 12. software responds by writing 11110b followed by the 2-bit slave address and a 1 (read) to the i2c data register. 13. if you want to read only one byte, soft ware responds by setting the nak bit of the i 2 c control register. 14. after the i 2 c controller shifts out the address bits mentioned in step 9 (2nd address transfer), the i 2 c slave sends an acknowledge by pulling the sda signal low during the next high period of scl. 15. the i 2 c controller sends the re peated start condition. 16. the i 2 c controller loads the i 2 c shift register with the contents of the i 2 c data register (third address transfer). 17. the i 2 c controller sends 11110b followed by the two most significant bits of the slave read address and a 1 (read). 18. the i 2 c slave sends an acknowledge by pulling the sda signal low during the next high period of scl. 19. the i 2 c controller shifts in a byte of data from the slave. 20. a receive interrupt is generated. 21. software responds by reading the i 2 c data register. 22. software responds by setting the stop bit of the i 2 c control register. 23. a nak condition is sent to the i 2 c slave. 24. a stop condition is sent to the i 2 c slave. i 2 c control register definitions i 2 c data register the i 2 c data register holds the data th at is to be loaded into the i 2 c shift register during a write to a slave. this register also holds data that is loaded from the i 2 c shift register dur-
ps019707-1003 p r e l i m i n a r y i2c controller z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 128 ing a read from a slave. the i 2 c shift register is not accessible in the register file address space, but only buffers incoming and outgoing data. i 2 c status register the read-only i 2 c status register indicates the status of the i 2 c controller. tdre?transmit data register empty when the i 2 c controller is enabled, this bit is 1 when the i 2 c data register is empty. when active, this bit causes the i 2 c controller to generate an interrupt, except when the i 2 c controller is shifting in data during the r eception of a byte or when shifting an address and the rd bit is set. writing to the i 2 cdata register clears this bit and the interrupt. rdrf?receive data register full this bit is set = 1 when the i 2 c controller is en abled and the i 2 c controller has received a byte of data. when asserted, this bit causes the i 2 c controller to generate an interrupt. reading the i 2 c data register clears this bit. ack?acknowledge this bit indicates the st atus of the acknowledge for the last byte transmitted or received. when set, this bit indicates th at an acknowledge was received for the last byte transmitted or received. table 68. i 2 c data register (i2cdata) bits 7 6 5 4 3 2 1 0 field data reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr f50h table 69. i 2 c status register (i2cstat) bits 7 6 5 4 3 2 1 0 field tdre rdrf ack 10b rd tas dss ncki reset 10000000 r/w rrrrrrrr addr f51h
ps019707-1003 p r e l i m i n a r y i2c controller z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 129 10b?10-bit address this bit indicates whether a 10- or 7-b it address is being transmitted. after the start bit is set, if the five most-significant bits of the address are 11110b , this bit is set. when set, it is reset once the first byte of the address has been sent. rd?read this bit indicates the direction of transfer of the data. it is active hi gh during a read. the status of this bit is determined by the least-significant bit of the i 2 c shift register after the start bit is set. tas?transmit address state this bit is active high while the ad dress is being shifted out of the i 2 c shift register. dss?data shift state this bit is active high while data is being shifted to or from the i 2 c shift register. ncki?nack interrupt this bit is set high when a not acknowledge condition is rece ived or sent and neither the start nor the stop bit is active. when set, th is bit generates an interrupt that can only be cleared by setting the start or stop bit, allowing the user to specify whether he wants to perform a stop or a repeated start . i 2 c control register the i 2 c control register enables the i 2 c operation. ien?i 2 c enable this bit enables the i 2 c transmitter and receiver. start?send start condition this bit sends the start condition. on ce asserted, it is cleared by the i 2 c controller after it sends the start condition or by deasserting the ien bit. if this bit is 1, it cannot be cleared to 0 by writing to the register. after this bit is set, the start condition is sent if there is data in the i 2 c data or i 2 c shift register. if there is no da ta in one of these registers, the i 2 c controller waits until data is load ed. if this bit is set while the i 2 c controller is shift- ing out data, it generates a st art condition after the byte shifts and the acknowledge table 70. i 2 c control register (i2cctl) bits 7 6 5 4 3 2 1 0 field ien start stop birq txi nak flush filten reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr f52h
ps019707-1003 p r e l i m i n a r y i2c controller z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 130 phase completes. if the stop bit is also set, it also waits until the stop condition is sent before the start condition. stop?send stop condition this bit causes the i 2 c controller to issue a stop co ndition after the byte in the i 2 c shift register has completed transmission or after a byte has been received in a receive opera- tion. once set, this bit is reset by the i 2 c controller after a stop co ndition has been sent or by deasserting the ien bit. if this bit is 1, it cannot be cleared to 0 by writing to the regis- ter. birq?baud rate genera tor interrupt request this bit causes an interrupt to occur every tim e the baud rate genera tor counts down to one. this bit allows the i 2 c controller to be used as an additional timer when the i 2 c con- troller is disabled. this bit is ignored when the i 2 c controller is enabled. txi?enable tdre interrupts this bit enables interrupts when the i 2 c data register is empty on the i 2 c controller. nak?send nak this bit sends a not acknowledge condition after the next byte of data has been read from the i 2 c slave. once asserted, it is deasserted after a not acknowledge is sent or the ien bit is deasserted. flush?flush data setting this bit to 1 clears the i 2 c data register and sets the tdre bit to 1. this bit allows flushing of the i 2 c data register when an nak is rece ived after the data has been sent to the i 2 c data register. reading th is bit always returns 0. filten?i 2 c signal filter enable setting this bit to 1 enables low-pass digita l filters on the sda and scl input signals. these filters reject any input pulse with period s less than a full system clock cycle. the fil- ters introduce a 3-system cloc k cycle latency on the inputs. i 2 c baud rate high and low byte registers the i 2 c baud rate high and low byte registers combine to form a 16 -bit reload value, brg[15:0], for the i 2 c baud rate generator. the i 2 c baud rate is calculated using the fol- lowing equation (note if brg = 0x0000, use 0x10000 in the equation): i2c baud rate (bits/s) system clock frequency (hz) 4 brg[15:0] ------------------- --------------------- --------------------- --------------- =
ps019707-1003 p r e l i m i n a r y i2c controller z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 131 . brh = i 2 c baud rate high byte most significant byte , brg[15:8], of the i 2 c baud rate generator?s reload value. if the diag bit in the i 2 c diagnostic control register is set to 1, a read of the i2cbrh register returns the current value of the i 2 c baud rate counter[15:8]. brl = i 2 c baud rate low byte least significant byte, brg[7:0], of the i 2 c baud rate generator?s reload value. if the diag bit in the i 2 c diagnostic control register is set to 1, a read of the i2cbrl register returns the current value of the i 2 c baud rate counter[7:0]. table 71. i 2 c baud rate high byte register (i2cbrh) bits 7 6 5 4 3 2 1 0 field brh reset 11111111 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr f53h table 72. i 2 c baud rate low by te register (i2cbrl) bits 7 6 5 4 3 2 1 0 field brl reset 11111111 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr f54h note:
ps019707-1003 p r e l i m i n a r y i2c controller z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 132 i 2 c diagnostic state register the i 2 c diagnostic state register provides observab ility of internal state. this is a read only register used for i 2 c diagnostics. sclin - value of serial clock input signal sdain - value of the se rial data input signal stpcnt - value of the internal stop count control signal txrxstate - value of the i 2 c state machine i 2 c diagnostic c ontrol register the i 2 c diagnostic register provides control over diagnostic modes. this is a read/write register used for i 2 c diagnostics. diag = diagnostic control bit - selects read back value of the baud rate reload regis- ters. in diagnostic mode the baud rate counter may be read back. 0 = normal mode 1 = diagnostic mode table 73. i 2 c diagnostic state register (i2cdst) bits 7 6 5 4 3 2 1 0 field sclin sdain stpcnt txrxstate reset x x 0 00000 r/w rrr r addr f55h table 74. i 2 c diagnostic control register (i2cdiag) bits 7 6 5 4 3 2 1 0 field reserved diag reset 00000000 r/w rrrrrrrr/w addr f56h
z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? ps019707-1003 p r e l i m i n a r y analog-to-digital converter 133 analog-to-digital converter overview the analog-to-digital converter (adc) converts an analog input signal to a 10-bit binary number. the features of the sigma-delta adc include: ? five analog input sources are multipl exed with general- purpose i/o ports ? interrupt upon conversion complete ? internal voltage re ference generator the adc is only available in the z8f0822, z8f0821, z8f0422 and z8f0421. architecture figure 29 illustrates the three major functional blocks (converter, analog multiplexer, and voltage reference generator) of the adc. the ad c converts an analog input signal to its digital representation. the 5-input analog mu ltiplexer selects one of the 5 analog input sources. the adc requires an input reference voltage for the conversion. the voltage ref- erence for the conversion may be input thro ugh the external vref pi n or generated inter- nally by the voltage reference generator.
ps019707-1003 p r e l i m i n a r y analog-to-digital converter z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 134 figure 29. analog-to-digital converter block diagram operation automatic power-down if the adc is idle (no conversions in progre ss) for 160 consecutive system clock cycles, portions of the adc are automatically powere d-down. from this power-down state, the adc requires 40 system clock cycles to po wer-up. the adc powers up when a conver- sion is requested using the adc control register. single-shot conversion when configured for single-shot conversion, the adc performs a single analog-to-digital conversion on the selected analog input chan nel. after completion of the conversion, the adc shuts down. the steps for setting up th e adc and initiating a single-shot conversion are as follows: analog-to-digital converter ana0 ana1 ana2 ana3 ana4 analog input multiplexer anain[3:0] internal voltage reference generator vref analog input reference input irq
ps019707-1003 p r e l i m i n a r y analog-to-digital converter z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 135 1. enable the desired analog inputs by configuring the general-purpose i/o pins for alternate function. this configuration disa bles the digital input and output drivers. 2. write to the adc control register to co nfigure the adc and begin the conversion. the bit fields in the adc control re gister can be written simultaneously: ? write to the anain[3:0] field to select one of the 5 analog input sources. ?clear cont to 0 to select a single-shot conversion. ? write to the vref bit to enable or disable the in ternal voltage reference generator. ?set cen to 1 to start the conversion. 3. cen remains 1 while the conversion is in progress. a single-shot conversion requires 5129 system clock cycles to complete. if a single-shot conversion is requested from an adc powered-down state, the adc uses 40 additional clock cycles to power-up before beginning the 5129 cycle conversion. 4. when the conversion is complete, the adc control logic performs the following operations: ? 10-bit data result written to {adcdh[7:0], adcdl[7:6]}. ? cen resets to 0 to indicate th e conversion is complete. ? an interrupt request is sent to the interrupt controller. 5. if the adc remains idle for 160 consecutive system clock cycles, it is automatically powered-down. continuous conversion when configured for continuous conversion , the adc continuously performs an analog- to-digital conversion on the sel ected analog input. each new data value over-writes the previous value stored in the adc data register s. an interrupt is generated after each con- version. in continuous mode, users must be aware that adc updates are lim- ited by the input signal bandwidth of the adc and the latency of the adc and its digital filter. step changes at th e input are not seen at the next output from the adc. the response of the adc (in all modes) is limited by the input signal bandwidth and the latency. the steps for setting up the adc and initiating continuous conversion are as follows: 1. enable the desired analog input by configuring the general-purpose i/o pins for alternate function. this disables th e digital input and output driver. 2. write to the adc control register to co nfigure the adc for continuous conversion. the bit fields in the adc control re gister may be written simultaneously: ? write to the anain[3:0] field to select one of the 5 analog input sources. caution:
ps019707-1003 p r e l i m i n a r y analog-to-digital converter z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 136 ?set cont to 1 to select continuous conversion. ? write to the vref bit to enable or disable the in ternal voltage reference generator. ?set cen to 1 to start the conversions. 3. when the first conversion in continuous operation is complete (after 5129 system clock cycles, plus the 40 cycles for powe r-up, if necessary), the adc control logic performs the following operations: ? cen resets to 0 to indicate the first conversion is complete. cen remains 0 for all subsequent conversions in continuous operation. ? an interrupt request is sent to the interrupt controller to indicate the conversion is complete. 4. thereafter, the adc writes a new 10-bit data result to {adcdh[7:0], adcdl[7:6]} every 256 system clock cycles. an interrupt request is sent to the interrupt controller when each conversion is complete. 5. to disable continuous conversion, clear the cont bit in the adc control register to 0. adc control register definitions adc control register the adc control register selects the analog input channel and initiates the analog-to-dig- ital conversion. cen?conversion enable 0 = conversion is complete. writing a 0 produc es no effect. the adc automatically clears this bit to 0 when a conversion has been completed. 1 = begin conversion. writing a 1 to this bit st arts a conversion. if a conversion is already in progress, the conversion restarts. this bit remains 1 until the conversion is complete. reserved?must be 0. table 75. adc control register (adcctl) bits 7 6 5 4 3 2 1 0 field cen reserved vref cont anain[3:0] reset 0010 0000 r/w r/w r/w r/w r/w r/w addr f70h
ps019707-1003 p r e l i m i n a r y analog-to-digital converter z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 137 vref 0 = internal reference generator enabled. the vref pin should be left unconnected or capacitively coupled to analog ground (avss). 1 = internal voltage re ference generator disabled. an exte rnal voltage reference must be provided through the vref pin. cont 0 = single-shot conversion. adc data is output once at completion of the 5129 system clock cycles. 1 = continuous conversion. adc data updated every 256 system clock cycles. anain?analog input select these bits select the analog inpu t for conversion. not all port pins in this list are available in all packages for the z8f082x family of pr oducts. refer to the signal and pin descrip- tions chapter for information rega rding the port pins available with each package style. do not enable unavailable analog inputs. 0000 = ana0 0001 = ana1 0010 = ana2 0011 = ana3 0100 = ana4 0101 = reserved. 011x = reserved. 1xxx = reserved. adc data high byte register the adc data high byte register contains th e upper eight bits of the 10-bit adc output. during a single-shot conversion, this value is invalid. access to the adc data high byte register is read-only. the full 10-b it adc result is given by {adcdh[7:0], adcdl[7:6]}. reading the adc data high byte register latches data in the adc low bits register. adcdh?adc data high byte this byte contains the upper eight bits of the 10-bit adc output. these bits are not valid table 76. adc data high byte register (adcdh) bits 7 6 5 4 3 2 1 0 field adcdh reset x r/w r addr f72h
ps019707-1003 p r e l i m i n a r y analog-to-digital converter z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 138 during a single-shot conversion. during a con tinuous conversion, the last conversion out- put is held in this register. the se bits are undefined after a reset. adc data low bits register the adc data low bits register contains the lower two bits of the conversion value. the data in the adc data low bits register is latched each time the adc data high byte reg- ister is read. reading this register always retu rns the lower two bits of the conversion last read into the adc high byte register. access to the adc data low bits register is read- only. the full 10-bit adc result is given by {adcdh[7:0], adcdl[7:6]}. adcdl?adc data low bits these are the least significant two bits of th e 10-bit adc output. these bits are undefined after a reset. reserved these bits are reserved and are always undefined. table 77. adc data low bits register (adcdl) bits 7 6 5 4 3 2 1 0 field adcdl reserved reset xx r/w rr addr f73h
z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? ps019707-1003 p r e l i m i n a r y flash memory 139 flash memory overview the products in the z8f082x family feature either 4kb (4096) or 8kb (8192 bytes) of non-volatile flash memory with read/write/e rase capability. the flash memory can be programmed and erased in-circuit by either user code or through the on-chip debugger. the flash memory array is arranged in 512-byte per page. the 512-byte page is the mini- mum flash block size that can be erased. the flash memory is also divided into 8 sectors which can be protected from programming and erase operations on a per sector basis. table 78 describes the flash memory configuration for each device in the z8f082x fam- ily. table 79 lists the sector address rang es. figure 30 illustrates the flash memory arrangement. table 78. flash memory configurations part number flash size number of pages program memory addresses sector size number of sectors pages per sector z8f04xx 4kb (4096) 8 0000h - 0fffh 0.5kb (512) 8 1 z8f08xx 8kb (8192) 16 0000h - 1fffh 1kb (1024) 8 2 table 79. flash memory sector addresses sector number flash sector address ranges z8f04xx z8f08xx 0 0000h-01ffh 0000h-03ffh 1 0200h-03ffh 0400h-07ffh 2 0400h-05ffh 0800h-0bffh 3 0600h-07ffh 0c00h-0fffh 4 0800h-09ffh 1000h-13ffh 5 0a00h-0bffh 1400h-17ffh 6 0c00h-0dffh 1800h-1bffh 7 0e00h-0fffh 1c00h-1fffh
ps019707-1003 p r e l i m i n a r y flash memory z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 140 figure 30. flash memory arrangement information area table 80 describes the z8f082x family informa tion area. this 512-byte information area is accessed by setting bit 7 of the flash page se lect register to 1. when access is enabled, the information area is mapp ed into program memory and overlays the 512 bytes at addresses fe00h to ffffh. when the information area access is enabled, ldc instruc- tions return data from the information area. cpu instruction fetches always comes from 8kb flash program memory 0000h 16 pages 512 bytes per page 01ffh 0200h 03ffh 1c00h 1dffh 1e00h 1fffh 0400h 05ffh 1a00h 1bffh addresses
ps019707-1003 p r e l i m i n a r y flash memory z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 141 program memory regardless of the information area access bi t. access to the information area is read-only. operation the flash controller provides the proper sign als and timing for byte programming, page erase, and mass erase of the flash memory. the flash controller contains a protection mechanism, via the flash control register (f ctl), to prevent accid ental programming or erasure. the following subsections provide details on the various operations (lock, unlock, sector protect, byte programm ing, page erase, and mass erase). timing using the flash frequency registers before performing a program or erase operati on on the flash memory, the user must first configure the flash frequency high and low byte registers. the flash frequency regis- ters allow programming and erasure of the fl ash with system clock frequencies ranging from 20khz through 20mhz (the valid range is limited to the device operating frequen- cies). the flash frequency high and low byte re gisters combine to form a 16-bit value, ffreq , to control timing for flash program an d erase operations. the 16-bit flash fre- quency value must contain the system clock frequency in khz. this value is calculated using the following equation:. flash programming and erasure are no t supported for system clock fre- quencies below 20khz, above 20mhz, or outside of the device operating frequency range. the flash frequency high and low byte registers must be loaded with the correct value to insure proper flash programming and erase operations. table 80. z8f082x family information area map program memory address (hex) function fe00h-fe3fh reserved fe40h-fe53h part number 20-character ascii alphanumeric code left justified and filled with zeros fe54h-ffffh reserved ffreq[15:0] system clock frequency (hz) 1000 --------------------- --------------------- ----------------- ----------------- = caution:
ps019707-1003 p r e l i m i n a r y flash memory z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 142 flash read protection the user code contained within the flash me mory can be protected from external access. programming the flash read protect option bit prevents reading of user code by the on- chip debugger or by using the flash controller bypass mode. refer to the option bits chapter and the on-chip debugger chapter for more information. flash write/erase protection the z8f082x family prov ides several levels of protectio n against accidental program and erasure of the flash memory contents. this pr otection is provided by the flash controller unlock mechanism, the flash sector protect register, and the flash write protect option bit. flash controller unlock mechanism at reset, the flash controller locks to preven t accidental program or erasure of the flash memory. to program or erase the flash memory , the flash controller must be unlocked. after unlocking the flash controller, the flash can be programmed or erased. any value written by user code to the flash control regi ster or flash page select register out of sequence will lock the flash controller. the proper steps to unlock the fl ash controller from user code are: 1. write 00h to the flash control register to reset the flash controller. 2. write the page to be programmed or er ased to the flash page select register. 3. write the first unlock command 73h to the flash control register. 4. write the second unlock command 8ch to the flash control register. 5. re-write the page writte n in step 2 to the flash page select register. flash sector protection the flash sector protect register can be configured to prevent sectors from being pro- grammed or erased. once a sector is protected, it cannot be unprotected by user code. the flash sector protect register will be cleare d after reset and any previously written protec- tion values will be lost. user code should write this register in their initialization routine if they want to enable sector protection. the flash sector protect register shares its register file address with the flash page select register. the flash sector protect regi ster is accessed by wr iting the flash control register with 5eh . once the flash sector protect register is selected, it can be accessed at the flash page select register address. when user code writes the flash sector protect register, bits can only be set to 1. thus, sec tors can be protected, but not unprotected, via register write operations. writing a value other than 5eh to the flash control register will de-select the flash sector protect register and re-enable access to the flash page select register.
ps019707-1003 p r e l i m i n a r y flash memory z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 143 the proper steps to setup the flash sector protect register from user code are: 1. write 00h to the flash control register to reset the flash controller. 2. write 5eh to the flash control register to sel ect the flash sector protect register. 3. read and/or write the flash sector protect register which is now at register file address ff9h . 4. write 00h to the flash control register to return the flash controller to its reset state. flash write protection option bit the flash write protect option bit can be en abled to block all program and erase opera- tions from user code. refer to the option bits chapter for mo re information. byte programming when the flash controller is unlocked, writ es to program memory from user code will program a byte into the flash if the address is located in the unlocked page. an erased flash byte contains all ones ( ffh ). the programming operation can only be used to change bits from one to zero. to change a flash bit (or multiple bits) from zero to one requires a page erase or mass erase operation. byte programming can be accomplished using the ez8 cpu?s ldc or ldci instructions. refer to the ez8 cpu user manual for a description of the ldc and ldci instructions. while the flash controller programs the flas h memory, the ez8 cpu idles but the system clock and on-chip peripherals continue to op erate. interrupts that occur when a program- ming operation is in progress will be servic ed once the programm ing operation is com- plete. to exit programming mode an d lock the flash controller, write 00h to the flash control register. user code cannot program flash memory on a page that lies in a protected sector. when user code writes memory locations, only addr esses located in the un locked page will be programmed. memory writes outside of the unlocked page are ignored. each memory location should not be programmed more than twice before an erase occurs. the proper steps to program the flash from user code are: 1. write 00h to the flash control register to reset the flash controller. 2. write the page of memory to be programmed to the flash page select register. 3. write the first unlock command 73h to the flash control register. 4. write the second unlock command 8ch to the flash control register. 5. re-write the page writte n in step 2 to the flash page select register. caution:
ps019707-1003 p r e l i m i n a r y flash memory z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 144 6. write program memory using ldc or ld ci instructions to program the flash. 7. repeat step 6 to program additional memory locations on the same page. 8. write 00h to the flash control register to lock the flash controller. page erase the flash memory can be erased one page (512 bytes) at a time. page erasing the flash memory sets all bytes in that page to the value ffh . the flash page select register identi- fies the page to be erased. while the flash controller executes the page erase operation, the ez8 cpu idles but the system clock and on -chip peripherals continue to operate. the ez8 cpu resumes operation after the page er ase operation complet es. interrupts that occur when the page erase opertion is in pr ogress will be serviced once the page erase operation is complete. when the page erase operation is complete, the flash controller returns to its locked state. only pages lo cated in unprotected sectors can be erased. the proper steps to perform a page erase operation are: 1. write 00h to the flash control register to reset the flash controller. 2. write the page to be erased to the flash page select register. 3. write the first unlock command 73h to the flash control register. 4. write the second unlock command 8ch to the flash control register. 5. re-write the page writte n in step 2 to the flash page select register. 6. write the page erase command 95h to the flash control register. mass erase the flash memory cannot be mass erased by user code. flash controller bypass the flash controller can be bypassed and the control signals for the flash memory brought out to the gpio pins. bypassing the flash controller allows faster programming algorithms by controlling the flash programming signals directly. flash controller bypass is recommended for gang programming applications and large volume customers who do not require in-c ircuit programming of the flash memory. please refer to the document entitled third-party flash programming support for z8 encore!? for more information on bypassing the flash controller. this document is available for download at www.zilog.com .
ps019707-1003 p r e l i m i n a r y flash memory z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 145 flash controller beh avior in debug mode the following changes in behavior of the fl ash controller occur when the flash control- ler is accessed using the on-chip debugger: ? the flash write protect option bit is ignored. ? the flash sector protect register is ig nored for programming and erase operations. ? programming operations are not limited to th e page selected in the flash page select register. ? bits in the flash sector protect regi ster can be written to one or zero. ? the second write of the flash page select re gister to unlock the flash controller is not necessary. ? the flash page select register can be writt en when the flash co ntroller is unlocked. ? the mass erase command is enabled. flash control register definitions flash control register the flash control register is used to unlock the flash controller for programming and erase operations, or to select the flash sector protect regi ster. the write-only flash con- trol register shares its register file addr ess with the read-only flash status register. fcmd?flash command 73h = first unlock command. 8ch = second unlock command. 95h = page erase command. 63h = mass erase command 5eh = flash sector protect register select. * all other commands, or any command out of sequence, will lock the flash controller. table 81. flash control register (fctl) bits 7 6 5 4 3 2 1 0 field fcmd reset 00000000 r/w wwwwwwww addr ff8h
ps019707-1003 p r e l i m i n a r y flash memory z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 146 flash status register the flash status register indicates the current state of the flash controller. this register can be read at any time. the read-only flash status register shares its register file address with the write-only flash control register. reserved these bits are reserved and must be 0. fstat?flash controller status 00_0000 = flash controller locked. 00_0001 = first unlock command received. 00_0010 = second unlock command received. 00_0011 = flash controller unlocked. 00_0100 = flash sector protect register selected. 00_1xxx = program operation in progress. 01_0xxx = page erase operation in progress. 10_0xxx = mass erase operation in progress. table 82. flash status register (fstat) bits 7 6 5 4 3 2 1 0 field reserved fstat reset 00000000 r/w rrrrrrrr addr ff8h
ps019707-1003 p r e l i m i n a r y flash memory z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 147 flash page select register the flash page select (fps) register selects the flash memory page to be erased or pro- grammed. each flash page contains 512 bytes of flash memory. during a page erase operation, all flash memory lo cations with the 7 most significant bits of the address given by the page field will be erased to ffh . the flash page select register shares its register file address with the flash sector pro- tect register. the flash page select regist er cannot be accessed when the flash sector protect register is enabled. info_en?informat ion area enable 0 = information area is not selected. 1 = information area is selected. the inform ation area is mapped into the program mem- ory address space at addresses fe00h through ffffh . page?page select this 7-bit field selects the flash memory page for programming and page erase opera- tions. program memory address[15:9] = page[6:0]. table 83. flash page se lect register (fps) bits 7 6 5 4 3 2 1 0 field info_en page reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr ff9h
ps019707-1003 p r e l i m i n a r y flash memory z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 148 flash sector protect register the flash sector protect register protects flash memory sectors from being programmed or erased from user code. the flash sector protect register shares its register file address with the flash page select register. the flash sector protect register can be accessed only after writing the flash control register with 5eh . user code can only write bits in this register to 1 (bits cannot be cleared to 0 by user code). sect n ?sector protect 0 = sector n can be programmed or erased from user code. 1 = sector n is protected and cannot be prog rammed or erased from user code. * user code can only write bits from 0 to 1. table 84. flash sector protect register (fprot) bits 7 6 5 4 3 2 1 0 field sect7 sect6 sect5 sect4 sect3 sect2 sect1 sect0 reset 00000000 r/w r/w1 r/w1 r/w1 r/w1 r/w1 r/w1 r/w1 r/w1 addr ff9h r/w1 = register is accessible for read operations. re gister can be written to 1 only (via user code).
ps019707-1003 p r e l i m i n a r y flash memory z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 149 flash frequency high a nd low byte registers the flash frequency high and low byte re gisters combine to form a 16-bit value, ffreq, to control timing for flash progra m and erase operations. the 16-bit flash fre- quency registers should be written with the system clock frequency in khz for program and erase operations. the flash frequency valu e is calculated usin g the following equa- tion: flash programming and erasure is not supported for system clock frequen- cies below 20khz, above 20mhz, or outside of the valid operating fre- quency range for the device. the fl ash frequency high and low byte registers must be loaded with the co rrect value to insure proper program and erase times. ffreqh and ffreql?flash frequency high and low bytes these 2 bytes, {ffreqh[7:0], ffreql[7:0]}, contain the 16-bit flash frequency value. table 85. flash frequency high byte register (ffreqh) bits 7 6 5 4 3 2 1 0 field ffreqh reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr ffah table 86. flash frequency low byte register (ffreql) bits 7 6 5 4 3 2 1 0 field ffreql reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr ffbh ffreq[15:0] ffreqh[7:0],ffreql[7:0] {} system clock frequency 1000 ---------------- ------------------ ------------------ ----------- == caution:
z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? ps019707-1003 p r e l i m i n a r y option bits 150 option bits overview option bits allow user configur ation of certain aspects of z8 f082x family operation. the feature configuration data is stored in pr ogram memory and read during reset. the fea- tures available for control through the option bits are: ? watch-dog timer time-out respon se selection?interrupt or reset. ? watch-dog timer enabled at reset. ? the ability to prevent unwant ed read access to user code in program memory. ? the ability to prevent accident al programming and erasure of all or a portion of the user code in program memory. ? voltage brown-out configuration-always en abled or disabled during stop mode to reduce stop mode power consumption. ? oscillator mode selection-for high, medium, and low power crystal oscillators, or external rc oscillator. operation option bit configuration by reset each time the option bits are programmed or erased, the device must be reset for the change to take place. during any reset operation (system reset, reset, or stop mode recovery), the option bits ar e automatically read from the program memory and written to option configuration registers. the option configuration registers control operation of the devices within the z8f082x family. option bit control is established before the device exits reset and the ez8 cpu begins code ex ecution. the option configuration registers are not part of the register file and are not accessible for read or write access. option bit address space the first two bytes of program memory at addresses 0000h and 0001h are reserved for the user programmable option bits. th e byte at program memory address 0000h config- ures user options. the byte at program memory address 0001h is reserved for future use and must be left in its unprogrammed state.
ps019707-1003 p r e l i m i n a r y option bits z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 151 program memory address 0000h wdt_res?watch-dog timer reset 0 = watch-dog timer time-out generates an inte rrupt request. interrupts must be globally enabled for the ez8 cpu to ackno wledge the interrupt request. 1 = watch-dog timer time-out causes a reset. this setting is the default for unpro- grammed (erased) flash. wdt_ao?watch-dog timer always on 0 = watch-dog timer is automatically enable d upon application of system power. watch- dog timer can not be disabled. 1 = watch-dog timer is enabled upon executi on of the wdt instruction. once enabled, the watch-dog timer can only be disabled by a reset or stop mode recovery. this set- ting is the default for un programmed (erased) flash. osc_sel[1:0]?oscillator mode selection 00 = on-chip oscillator configured for use with external rc networks (<4mhz). 01 = minimum power for use with very lo w frequency crystals (32khz to 1.0mhz). 10 = medium power for use with medium fre quency crystals or ceramic resonators (0.5mhz to 10.0mhz). 11 = maximum power for use with high frequ ency crystals (8.0mhz to 20.0mhz). this setting is the default for un programmed (erased) flash. vbo_ao?voltage brown-out protection always on 0 = voltage brown-out protection is disabled in stop mode to reduce total power con- sumption. 1 = voltage brown-out protection is always enabled including during stop mode. this setting is the default for un programmed (erased) flash. rp?read protect 0 = user program code is inaccessible. limite d control features are available through the on-chip debugger. 1 = user program code is accessible. all on-chip debugger commands are enabled. this setting is the default for un programmed (erased) flash. table 87. option bits at program memory address 0000h bits 7 6 5 4 3 2 1 0 field wdt_res wdt_ao osc_sel[1:0] vbo_ao rp fhswp fwp reset u r/w r/w addr program memory 0000h note: u = unchanged by reset. r/w = read/write.
ps019707-1003 p r e l i m i n a r y option bits z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 152 fhswp?flash high sector write protect fwp?flash write protect these two option bits combine to provide 3 levels of program memory protection: program memory address 0001h reserved these option bits are reserved for future use and must always be 1. this setting is the default for unprogram med (erased) flash. fhswp fwp description 0 0 programming and erasure disabled for all of program memory. programming, page erase, and mass eras e via user code is disabled. mass erase is available through the on-chip debugger. 1 0 programming and page erase are en abled for the high sector of the program memory only. the high sector on the z8f082x family products contains 512 to 1024 bytes of flash with addresses at the top of the available flash memory. programming and page erase are disabled for the other portions of the program memory. mass erase through user code is disabled. mass erase is available through the on-chip debugger. 0 or 1 1 programming, page erase, and mass erase are enabled for all of program memory. table 88. options bits at program memory address 0001h bits 7 6 5 4 3 2 1 0 field reserved reset u r/w r/w addr program memory 0001h note: u = unchanged by reset. r/w = read/write.
z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? ps019707-1003 p r e l i m i n a r y on-chip debugger 153 on-chip debugger overview the z8f082x family products have an integrated on-chip debugger (ocd) that provides advanced debugging features including: ? reading and writing of the register file ? reading and writing of program and data memory ? setting of breakpoints ? execution of ez8 cpu instructions. architecture the on-chip debugger consists of four primary functional blocks: transmitter, receiver, auto-baud generator, an d debug controller. figure 31 illust rates the architecture of the on- chip debugger figure 31. on-chip debugger block diagram auto-baud system clock transmitter receiver dbg pin debug controller ez8 cpu control detector/generator
ps019707-1003 p r e l i m i n a r y on-chip debugger z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 154 operation ocd interface the on-chip debugger uses the dbg pin for communication with an external host. this one-pin interface is a bi-directional open-drain interface that transmits and receives data. data transmission is half-duplex, in that tr ansmit and receive cannot occur simultaneously. the serial data on the dbg pin is sent using the standard asynchronous data format defined in rs-232. this pin can interface the z8f082x fa mily products to the serial port of a host pc using minimal external hardware.two di fferent methods for connecting the dbg pin to an rs-232 interface are depicted in figures 32 and 33. for operation of the on-chip debugger, all power pins (vdd and avdd) must be supplied with power, and all ground pins (vss and avss) must be properly grounded. the dbg pin is open-drain and must al ways be connected to vdd through an external pull-up resistor to insure proper operation. figure 32. interfacing the on-chip debugger ?s dbg pin with an rs-232 interface (1) caution: rs-232 tx rs-232 rx rs-232 transceiver v dd dbg pin 10k ohm diode
ps019707-1003 p r e l i m i n a r y on-chip debugger z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 155 figure 33. interfacing the on-chip debugger ?s dbg pin with an rs-232 interface (2) debug mode the operating characteristics of the z8f0 82x family devices in debug mode are: ? the ez8 cpu fetch unit stops, idling the ez 8 cpu, unless directed by the ocd to execute specific instructions. ? the system clock operates unless in stop mode. ? all enabled on-chip peripherals operate unless in stop mode. ? automatically exits halt mode. ? constantly refreshes the watch-dog timer, if enabled. entering debug mode the device enters debug mode following any of the following operations: ? writing the dbgmode bit in the ocd control register to 1 using the ocd interface. ? ez8 cpu execution of a brk (breakpoint) instruction. ? match of pc to ocdcntr register (when enabled) ? ocdcntr register decrements to 0000h (when enabled) ? if the dbg pin is low when the device exits reset, the on-chip debugger automatically puts the device into debug mode. exiting debug mode the device exits debug mode following any of the following operations: ? clearing the dbgmode bit in the ocd control register to 0. rs-232 tx rs-232 rx rs-232 transceiver v dd dbg pin 10k ohm open-drain buffer
ps019707-1003 p r e l i m i n a r y on-chip debugger z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 156 ? power-on reset ? voltage brown-out reset ? asserting the reset pin low to initiate a reset. ? driving the dbg pin low while the devi ce is in stop mode initiates a system reset. ocd data format the ocd interface uses the asynchronous data format defined for rs-232. each character is transmitted as 1 start bit, 8 data bits (least-s ignificant bit first), and 1 stop bit (figure 34) figure 34. ocd data format ocd auto-baud detector/generator to run over a range of baud rates (bits per second) with various system clock frequencies, the on-chip debugger has an auto-baud dete ctor/generator. after a reset, the ocd is idle until it receives data. the ocd requires that the first character sent from the host is the character 80h . the character 80h has eight continuous bits low (one start bit plus 7 data bits). the auto-baud detector measures this period and sets the ocd baud rate generator accordingly. the auto-baud detector/generator is clocke d by the system clock. the minimum baud rate is the system clock frequency divided by 512. for optimal operation, the maximum recommended baud rate is the system clock frequency divided by 8. the theoretical maxi- mum baud rate is the system clock frequency divided by 4. this theoretical maximum is possible for low noise design s with clean signals. table 89 lists minimum and recom- mended maximum baud rates fo r sample crystal frequencies. table 89. ocd baud-rate limits system clock frequency (mhz) recommended maximum baud rate (kbits/s) minimum baud rate (kbits/s) 20.0 2500 39.1 1.0 125.0 1.96 0.032768 (32khz) 4.096 0.064 startd0d1d2d3d4d5d6d7stop
ps019707-1003 p r e l i m i n a r y on-chip debugger z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 157 if the ocd receives a serial break (nine or more continuous bits low) the auto-baud detector/generator resets. th e auto-baud detector/generator can then be reconfigured by sending 80h . ocd serial errors the on-chip debugger can detect any of the following error conditions on the dbg pin: ? serial break (a minimum of nine continuous bits low) ? framing error (received stop bit is low) ? transmit collision (ocd and ho st simultaneous transmissi on detected by the ocd) when the ocd detects one of these errors, it aborts any command currently in progress, transmits a serial break 4096 system clock cycles long back to the host, and resets the auto-baud detector/generator. a framing er ror or transmit collision may be caused by the host sending a serial break to the ocd. be cause of the open-drain nature of the inter- face, returning a serial break break back to th e host only extends the length of the serial break if the host releases the serial break early. the host should transmit a serial break on the dbg pin when first connecting to the z8f082x family device or when recovering from an error. a serial break from the host resets the auto-baud generator/detector bu t does not reset the ocd control register. a serial break leaves the device in debug mode if that is the current mode. the ocd is held in reset until the end of the serial brea k when the dbg pin returns high. because of the open-drain nature of the dbg pin, the host can send a serial break to the ocd even if the ocd is transmitting a character. breakpoints execution breakpoints are generated using the brk instruction (opcode 00h ). when the ez8 cpu decodes a brk instruction, it signal s the on-chip debugger. if breakpoints are enabled, the ocd idles the ez8 cpu and enters debug mode. if breakpoints are not enabled, the ocd ignores the brk signal an d the brk instruction operates as an nop. if breakpoints are enabled, the ocd can be configured to automa tically enter debug mode, or to loop on the break instruction. if the ocd is configured to loop on the brk instruction, then th e cpu is still enabled to servic e dma and interrupt requests. the loop on brk instruction can be used to service interrupts in the background. for interrupts to be serviced in the background, there cannot be any breakpoints in the inter- rupt service routine. otherwise, the cpu stops on the breakpoint in the interrupt routine. for interrupts to be serviced in the background, interrupts mu st also be enabled. debug- ging software should not auto matically enable interrupts when using this feature, since interrupts are typically disabled during criti cal sections of code where interrupts should not occur (such as adjusting the stack pointer or modifying shared data).
ps019707-1003 p r e l i m i n a r y on-chip debugger z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 158 software can poll the idle bit of the ocdstat register to determine if the ocd is loop- ing on a brk instruction. when software want s to stop the cpu on the brk instruction it is looping on, software shou ld not set the dbgmode bit of the ocdctl register. the cpu may have vectored to and be in the middle of an interrupt service routine when this bit gets set. instead, software should clear the brklp bit. this allows the cpu to finish the interrupt service routine it may be in and return the brk instru ction. when the cpu returns to the brk instruction it was previo usly looping on, it automatically sets the dbgmode bit and enter debug mode. software should also note that the majority of the ocd commands are still disabled when the ez8 cpu is looping on a brk instruction. the ez8 cpu must be stopped and the part must be in debug mode before these commands can be issued. breakpoints in flash memory the brk instruc tion is opcode 00h , which corresponds to the fu lly programmed state of a byte in flash memory. to implement a breakpoint, write 00h to the desired address, over- writing the current instruction. to remove a breakpoint, the correspon ding page of flash memory must be erased and reprogrammed with the original data. ocdcntr register the on-chip debugger contains a multipurpose 16-bit counter register . it can be used for the following: ? count system clock cycles between breakpoints. ? generate a brk when it counts down to zero. ? generate a brk when its valu e matches the program counter. when configured as a counter, the ocdcntr register starts counting when the on-chip debugger leaves debug mode and stops coun ting when it enters debug mode again or when it reaches the maximum count of ffffh . the ocdcntr register automatically resets itself to 0000h when the ocd exits debug mode if it is configured to count clock cycles between breakpoints. the ocdcntr register is used by ma ny of the ocd commands. it counts the number of bytes for the register and memory read/w rite commands. it holds the residual value when generating the crc. therefore, if the ocd- cntr is being used to ge nerate a brk, its value sh ould be written as a last step before leaving debug mode. since this register is overwritten by variou s ocd commands, it shou ld only be used to generate temporary breakpoints, such as steppi ng over call instructio ns or running to a specific instruction and stopping. caution:
ps019707-1003 p r e l i m i n a r y on-chip debugger z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 159 on-chip debugger commands the host communicates to the on-chip debugger by sending ocd commands using the dbg interface. during normal operation, on ly a subset of the ocd commands are avail- able. in debug mode, all ocd commands beco me available unless the user code and control registers are protected by progr amming the read protect option bit ( rp ). the read protect option bit prevents the code in memory from being read out of the z8f082x family products. when this option is enabled, several of the ocd commands are disabled. table 90 contains a summary of the on-chip debugger commands. each ocd command is described in further deta il in the bulleted list following table 90. table 90 indicates those commands that op erate when the device is not in debug mode (normal operation) and those commands that are disabled by programming the read protect option bit. table 90. on-chip debugger commands debug command command byte enabled when not in debug mode? disabled by read protect option bit read ocd revision 00h yes - write ocd counter register 01h - - read ocd status register 02h yes - read ocd counter register 03h - - write ocd control register 04h yes cannot clear dbgmode bit read ocd control register 05h yes - write program counter 06h - disabled read program counter 07h - disabled write register 08h - only writes of the flash memory control registers are allowed. additionally, only the mass erase command is allowed to be written to the flash control register. read register 09h - disabled write program memory 0ah - disabled read program memory 0bh - disabled write data memory 0ch - yes read data memory 0dh - - read program memory crc 0eh - - reserved 0fh - - step instruction 10h - disabled
ps019707-1003 p r e l i m i n a r y on-chip debugger z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 160 in the following bulleted list of ocd comman ds, data and commands sent from the host to the on-chip debugger are identified by ? dbg command/data ?. data sent from the on-chip debugger back to the host is identified by ? dbg data ? ? read ocd revision (00h) ?the read ocd revision command determines the version of the on-chip debugger. if ocd commands are added, removed, or changed, this revisi on number changes. dbg 00h dbg ocdrev[15:8] (major revision number) dbg ocdrev[7:0] (minor revision number) ? write ocd counter register (01h) ?the write ocd counter register command writes the data that follows to the ocdcnt r register. if the device is not in debug mode, the data is discarded. dbg 01h dbg ocdcntr[15:8] dbg ocdcntr[7:0] ? read ocd status register (02h) ?the read ocd status register command reads the ocdstat register. dbg 02h dbg ocdstat[7:0] ? read ocd counter register (03h) ?the ocd counter register can be used to count system clock cycles in between brea kpoints, generate a brk when it counts down to zero, or generate a brk when its value matches the program counter. since this register is really a down counter, the re turned value is inverted when this register is read so the returned result appears to be an up counter. if th e device is not in debug mode, this command returns ffffh. dbg 03h dbg ~ocdcntr[15:8] dbg ~ocdcntr[7:0] ? write ocd control register (04h) ?the write ocd control register command writes the data that follows to the ocdctl register. when the read protect option bit is enabled, the dbgmode bit (ocdctl[7]) can only be set to 1, it cannot be stuff instruction 11h - disabled execute instruction 12h - disabled reserved 13h - ffh - - table 90. on-chip debugger commands debug command command byte enabled when not in debug mode? disabled by read protect option bit
ps019707-1003 p r e l i m i n a r y on-chip debugger z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 161 cleared to 0 and the only method of puttin g the device back into normal operating mode is to reset the device. dbg 04h dbg ocdctl[7:0] ? read ocd control register (05h) ?the read ocd control register command reads the value of the ocdctl register. dbg 05h dbg ocdctl[7:0] ? write program counter (06h) ?the write program counter command writes the data that follows to the ez8 cpu?s progr am counter (pc). if the device is not in debug mode or if the read protect option bit is enabled, the program counter (pc) values are discarded. dbg 06h dbg programcounter[15:8] dbg programcounter[7:0] ? read program counter (07h) ?the read program counter command reads the value in the ez8 cpu?s program counter (p c). if the device is not in debug mode or if the read protect option bit is enabled, this command returns ffffh . dbg 07h dbg programcounter[15:8] dbg programcounter[7:0] ? write register (08h) ?the write register command writes data to the register file. data can be written 1-256 bytes at a time (256 bytes can be written by setting size to zero). if the device is not in debug mode , the address and data values are discarded. if the read protect option bit is enabled, then only writes to the flash control registers are allowed and all other register write data values are discarded. dbg 08h dbg {4?h0,register address[11:8]} dbg register address[7:0] dbg size[7:0] dbg 1-256 data bytes ? read register (09h) ?the read register command reads data from the register file. data can be read 1-256 bytes at a time (256 bytes can be read by setting size to zero). if the device is not in debug mode or if the read protect option bit is enabled, this command returns ffh for all the data values. dbg 09h dbg {4?h0,register address[11:8] dbg register address[7:0] dbg size[7:0] dbg 1-256 data bytes
ps019707-1003 p r e l i m i n a r y on-chip debugger z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 162 ? write program memory (0ah) ?the write program memory command writes data to program memory. this command is equiva lent to the ldc and ldci instructions. data can be written 1-65536 bytes at a time (65536 bytes can be written by setting size to zero). the on-chip flash controller mu st be written to and unlocked for the programming operation to occur. if the flas h controller is not unlocked, the data is discarded. if the device is not in debug mo de or if the read protect option bit is enabled, the data is discarded. dbg 0ah dbg program memory address[15:8] dbg program memory address[7:0] dbg size[15:8] dbg size[7:0] dbg 1-65536 data bytes ? read program memory (0bh) ?the read program memo ry command reads data from program memory. this command is equivalent to the ldc and ldci instructions. data can be read 1-65536 bytes at a time (65536 bytes can be read by setting size to zero). if the device is not in debug mode or if the read protect option bit is enabled, this command returns ffh for the data. dbg 0bh dbg program memory address[15:8] dbg program memory address[7:0] dbg size[15:8] dbg size[7:0] dbg 1-65536 data bytes ? write data memory (0ch) ?the write data memory co mmand writes data to data memory. this command is equivalent to th e lde and ldei instructions. data can be written 1-65536 bytes at a time (65536 bytes ca n be written by setting size to 0). if the device is not in debug mode or if the read protect option bit is enabled, the data is discarded. dbg 0ch dbg data memory address[15:8] dbg data memory address[7:0] dbg size[15:8] dbg size[7:0] dbg 1-65536 data bytes ? read data memory (0dh) ?the read data memory command reads from data memory. this command is equivalent to th e lde and ldei instructions. data can be read 1-65536 bytes at a time (65536 bytes can be read by setting size to 0). if the device is not in debug mode, this command returns ffh for the data. dbg 0dh dbg data memory address[15:8] dbg data memory address[7:0] dbg size[15:8]
ps019707-1003 p r e l i m i n a r y on-chip debugger z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 163 dbg size[7:0] dbg 1-65536 data bytes ? read program memory crc (0eh) ?the read program memory crc command computes and returns the crc (cyclic redu ndancy check) of program memory using the 16-bit crc-ccitt polynomial. if the de vice is not in debug mode, this command returns ffffh for the crc value. unlike most other ocd read commands, there is a delay from issuing of the command until the ocd returns the data. the ocd reads the program memory, calculates the crc value, and returns the result. the delay is a function of the progra m memory size and is approximately equal to the system clock period multiplied by th e number of bytes in the program memory. dbg 0eh dbg crc[15:8] dbg crc[7:0] ? step instruction (10h) ?the step instruction co mmand steps one assembly instruction at the current program counte r (pc) location. if the device is not in debug mode or the read protect option bit is enabled, the ocd ignores this command. dbg 10h ? stuff instruction (11h) ?the stuff instruction command steps one assembly instruction and allows specification of the fi rst byte of the instruction. the remaining 0-4 bytes of the instruction are read from program memory. this command is useful for stepping over instructions where the first byte of the in struction has been overwritten by a breakpoint. if the device is not in debug mode or the read protect option bit is enabled, the ocd ignores this command. dbg 11h dbg opcode[7:0] ? execute instruction (12h) ?the execute instruction command allows sending an entire instruction to be executed to the ez 8 cpu. this command can also step over breakpoints. the number of bytes to send for the instruction depends on the opcode. if the device is not in debug mode or the re ad protect option bit is enabled, the ocd ignores this command dbg 12h dbg 1-5 byte opcode on-chip debugger control register definitions ocd control register the ocd control register controls the state of the on-chip debugger. this register enters or exits debug mode and enables the brk in struction. it can also reset the z8f082x family device.
ps019707-1003 p r e l i m i n a r y on-chip debugger z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 164 a ?reset and stop? function can be achieved by writing 81h to this register. a ?reset and go? function can be achieved by writing 41h to this register. if the device is in debug mode, a ?run? function can be implemented by writing 40h to this register. dbgmode?debug mode setting this bit to 1 causes the device to en ter debug mode. when in debug mode, the ez8 cpu stops fetching new instructions. clea ring this bit causes the ez8 cpu to start running again. this bit is au tomatically set when a brk inst ruction is decoded and break- points are enabled. if the read protect option bit is enabled, this bit can only be cleared by resetting the device, it cannot be written to 0. 0 = the z8f082x family device is operating in normal mode. 1 = the z8f082x family device is in debug mode. brken?breakpoint enable this bit controls the behavior of the brk instruction (opcode 00h). by default, break- points are disabled and the brk instruction beha ves like a nop. if this bit is set to 1 and a brk instruction is decoded, the ocd take s action dependent upon the brkloop bit. 0 = brk instruction is disabled. 1 = brk instruction is enabled. dbgack?debug acknowledge this bit enables the debug acknowledge feature. if this bit is set to 1, then the ocd sends an debug acknowledge character ( ffh ) to the host when a breakpoint occurs. 0 = debug acknowledge is disabled. 1 = debug acknowledge is enabled. brkloop?breakpoint loop this bit determines what ac tion the ocd takes when a brk instruction is decoded if breakpoints are enabled (brken is 1). if this bit is 0, then the dbgmode bit is automat- ically set to 1 and the ocd enterd debug mo de. if brkloop is set to 1, then the ez8 cpu loops on the brk instruction. 0 = brk instruction sets dbgmode to 1. 1 = ez8 cpu loops on brk instruction. brkpc?break when pc == ocdcntr if this bit is set to 1, then the ocdcntr regi ster is used as a hardware breakpoint. when the program counter matches the value in the ocdcntr register, dbgmode is auto- table 91. ocd control register (ocdctl) bits 7 6 5 4 3 2 1 0 field dbgmode brken dbgack brkloop brkpc brkzro reserved rst reset 00000000 r/w r/w r/w r/w r r r r r/w
ps019707-1003 p r e l i m i n a r y on-chip debugger z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 165 matically set to 1. if this bit is set, the ocdcntr register does not count when the cpu is running. 0 = ocdcntr is setup as counter 1 = ocdcntr generates hardware break when pc == ocdcntr brkzro?break when ocdcntr == 0000h if this bit is set, then the ocd automatically sets the dbgmode bit when the ocd- cntr register counts down to 0000h . if this bit is set, the ocdcntr register is not reset when the part leaves debug mode. 0 = ocd does not generate brk when ocdcntr decrements to 0000h 1 = ocd sets dbgmode to 1 when ocdcntr decrements to 0000h reserved these bits are reserved and must be 0. rst?reset setting this bit to 1 resets the z8f082x family device. the device goes through a normal power-on reset sequence with the exception th at the on-chip debugger is not reset. this bit is automatically cleared to 0 when the reset finishes. 0 = no effect. 1 = reset the z8f082x family device. ocd status register the ocd status register reports status inform ation about the current state of the debugger and the system. idle?cpu idling this bit is set if the part is in debug mo de (dbgmode is 1), or if a brk instruction occurred since the last time oc dctl was written. this can be used to determine if the cpu is running or if it is idling. 0 = the ez8 cpu is running. 1 = the ez8 cpu is either stopped or looping on a brk instruction. halt?halt mode 0 = the device is not in halt mode. 1 = the device is in halt mode. table 92. ocd status register (ocdstat) bits 7 6 5 4 3 2 1 0 field idle halt rpen reserved reset 00000000 r/w rrrrrrrr
ps019707-1003 p r e l i m i n a r y on-chip debugger z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 166 rpen?read protect option bit enabled 0 = the read protect option bit is disabled (1). 1 = the read protect option bit is enab led (0), disabling many ocd commands. reserved. must be 0.
z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? ps019707-1003 p r e l i m i n a r y on-chip oscillator 167 on-chip oscillator overview the products in the z8f082x family feature an on-chip oscillator for use with external crystals with frequencies from 32khz to 20mhz. in addition, the oscillator can support external rc networks with osc illation frequencies up to 4mhz or ceramic resonators with frequencies up to 20mhz. this oscillator generates the primar y system clock for the inter- nal ez8 cpu and the majority of the on-c hip peripherals. alternatively, the x in input pin can also accept a cmos-level clock input si gnal (32khz?20mhz). if an external clock generator is used, the x out pin must be left unconnected. when configured for use with cr ystal oscillators or external cl ock drivers, the frequency of the signal on the x in input pin determines the frequency of the system clock (that is, no internal clock divider). in rc operation, the system clock is driven by a clock divider (divide by 2) to ensure 50% duty cycle. operating modes the z8f082x family products suppor t four different oscillator modes: ? on-chip oscillator configured for use with external rc networks (<4mhz). ? minimum power for use with very low fre quency crystals (32khz to 1.0mhz). ? medium power for use with medium frequ ency crystals or ceramic resonators (0.5mhz to 10.0mhz). ? maximum power for use with high frequency crystals or ceramic resonators (8.0mhz to 20.0mhz). the oscillator mode is selected using user-p rogrammable option bits. please refer to the option bits chapter for information. crystal oscillator operation figure 35 illustrates a recomm ended configuration for connec tion with an external funda- mental-mode, parallel-resonant crystal oper ating at 20mhz. recommended 20mhz crys- tal specifications are provided in table 93. resistor r 1 is optional and limits total power dissipation by the crystal. printed circuit bo ard layout should add no more than 4pf of
ps019707-1003 p r e l i m i n a r y on-chip oscillator z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 168 stray capacitance to either the x in or x out pins. if oscillation does not occur, reduce the values of capacitors c 1 and c 2 to decrease loading. figure 35. recommended 20mhz crys tal oscillator configuration table 93. recommended crystal oscillat or specifications (20mhz operation) parameter value units comments frequency 20 mhz resonance parallel mode fundamental series resistance (r s )25 w maximum load capacitance (c l )20 pf maximum shunt capacitance (c 0 ) 7 pf maximum drive level 1 mw maximum c2 = 22pf c1 = 22pf crystal xout xin on-chip oscillator r1 = 220 ?
ps019707-1003 p r e l i m i n a r y on-chip oscillator z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 169 oscillator operation with an external rc network figure 36 illustrates a recomm ended configuration for connec tion with an external resis- tor-capacitor (rc) network. figure 36. connecting the on-chip osc illator to an external rc network an external resistance value of 15k ? is recommended for osc illator operation with an external rc network. the minimum resist ance value to ensure operation is 10k ?. the typical oscillator frequency can be esti mated from the values of the resistor ( r in k ? ) and capacitor ( c in pf) elements usi ng the following equation: figure 37 illustrates the typical (3.3v and 25 0 c) oscillator frequency as a function of the capacitor ( c in pf) employed in the rc network assuming a 15k ? external resistor. for very small values of c, the pa rasitic capacitance of the osc illator xin pin and the printed circuit board should be included in the estimation of the oscillator frequency. c x in r v dd oscillator frequency (khz) 1 6 10 1.5 rc () ------------------ -------------- =
ps019707-1003 p r e l i m i n a r y on-chip oscillator z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 170 figure 37. typical rc oscillator frequency as a function of the external capacitance with a 15k ? resistor 0 100 200 300 400 500 600 700 800 900 1000 0 100 200 300 400 500 600 700 800 900 1000 c (pf) f (khz)
z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? ps019707-1003 p r e l i m i n a r y electrical characteristics 171 electrical characteristics all data in this chapter is pre-qualificatio n and pre-characterization and is subject to change. absolute maximum ratings stresses greater than those listed in table 94 may cause permanent damage to the device. these ratings are stress ratings only. operation of the device at any condition outside those indicated in the operational s ections of these specifications is not implied. exposure to absolute maximum rating cond itions for extended periods may affect device reliability. for improved reliability, unused inputs must be tied to one of the supply voltages (v dd or v ss ). table 94. absolute maximum ratings parameter minimum maximum units notes ambient temperature under bias -40 +105 c 1 storage temperature ?65 +150 c voltage on any pin with respect to v ss ?0.3 +5.5 v 2 voltage on av ss pin with respect to v ss ?0.3 +0.3 v 2 voltage on v dd pin with respect to v ss ?0.3 +3.6 v voltage on av dd pin with respect to v dd ?0.3 +0.3 v maximum current on input and/or inactive output pin ?5 +5 a maximum output current from active output pin -25 +25 ma 20-pin ssop package maximum ratings at 0 0 c to 70 0 c total power dissipation 430 mw maximum current into v dd or out of v ss 120 ma notes: 1. this voltage applies to all pins except the following: vdd, avdd, vref, pins supporting analog input (port b), and where noted otherwise. caution:
ps019707-1003 p r e l i m i n a r y electrical characteristics z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 172 20-pin ssop package maximum ratings at 70 0 c to 105 0 c total power dissipation 250 mw maximum current into v dd or out of v ss 69 ma 20-pin pdip package maximum ratings at 0 0 c to 70 0 c total power dissipation 775 mw maximum current into v dd or out of v ss 215 ma 20-pin pdip package maximum ratings at 70 0 c to 105 0 c total power dissipation 285 mw maximum current into v dd or out of v ss 79 ma 28-pin soic package maximum ratings at 0 0 c to 70 0 c total power dissipation 450 mw maximum current into v dd or out of v ss 125 ma 28-pin soic package maximum ratings at 70 0 c to 105 0 c total power dissipation 260 mw maximum current into v dd or out of v ss 73 ma 28-pin pdip package maximum ratings at 0 0 c to 70 0 c total power dissipation 1100 mw maximum current into v dd or out of v ss 305 ma 28-pin pdip package maximum ratings at 70 0 c to 105 0 c total power dissipation 400 mw maximum current into v dd or out of v ss 110 ma table 94. absolute maximum ratings (continued) parameter minimum maximum units notes notes: 1. this voltage applies to all pins except the following: vdd, avdd, vref, pins supporting analog input (port b), and where noted otherwise.
ps019707-1003 p r e l i m i n a r y electrical characteristics z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 173 dc characteristics table 95 lists the dc characteri stics of the z8f082 x family products. all voltages are ref- erenced to v ss , the primary system ground. table 95. dc characteristics symbol parameter t a = -40 0 c to 105 0 c units conditions minimum typical maximum v dd supply voltage 2.7 ? 3.6 v v il1 low level input voltage -0.3 ? 0.3*v dd v for all input pins except reset , dbg, and xin. v il2 low level input voltage -0.3 ? 0.2*v dd v for reset , dbg, and xin. v ih1 high level input voltage 0.7*v dd ? 5.5 v ports a and c pins when their programmable pull-ups are disabled. v ih2 high level input voltage 0.7*v dd ? v dd +0.3 v port b pins. v ih3 high level input voltage 0.8*v dd ? v dd +0.3 v reset , dbg, and xin pins. v ol1 low level output voltage ? ? 0.4 v i ol = 2ma; vdd = 3.0v high output drive disabled. v oh1 high level output voltage 2.4 ?? v i oh = -2ma; vdd = 3.0v high output drive disabled. v ol2 low level output voltage high drive ?? 0.6 v i ol = 20ma; vdd = 3.3v high output drive enabled t a = -40 0 c to +70 0 c v oh2 high level output voltage high drive 2.4 ?? v i oh = -20ma; vdd = 3.3v high output drive enabled; t a = -40 0 c to +70 0 c v ol3 low level output voltage high drive ?? 0.6 v i ol = 15ma; vdd = 3.3v high output drive enabled; t a = +70 0 c to +105 0 c v oh3 high level output voltage high drive 2.4 ?? v i oh = 15ma; vdd = 3.3v high output drive enabled; t a = +70 0 c to +105 0 c i il input leakage current -5 ? +5 a v dd = 3.6v; v in = vdd or vss 1 i tl tri-state leakage current -5 ? +5 a v dd = 3.6v c pad gpio port pad capacitance ? 8.0 2 ? pf c xin xin pad capacitance ? 8.0 2 ? pf
ps019707-1003 p r e l i m i n a r y electrical characteristics z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 174 figure 38 illustrates the typical current consumption while oper ating at 25oc, 3.3v, versus the system clock frequency. c xout xout pad capacitance ? 9.5 2 ? pf i pu1 weak pull-up current 92050 a vdd = 2.7 - 3.6v. t a = 0 0 c to +70 0 c i pu2 weak pull-up current 72075 a vdd = 2.7 - 3.6v. t a = -40 0 c to +105 0 c i ccs1 supply current in stop mode with vbo enabled 600 a v dd = 2.7v; 25 0 c i ccs2 supply current in stop mode with vbo disabled 2 a v dd = 2.7v; 25 0 c i ccs3 supply current in stop mode with vbo and wdt disabled 1 a v dd = 2.7v; 25 0 c 1 this condition excludes all pins that have on-chip pull-ups, when driven low. 2 these values are provided for design guidance only and are not tested in production. table 95. dc characteristics symbol parameter t a = -40 0 c to 105 0 c units conditions minimum typical maximum
ps019707-1003 p r e l i m i n a r y electrical characteristics z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 175 stics figure 39 illustrates the typical current cons umption in halt mode while operating at 25oc, 3.3v, versus the system clock frequency. figure 38. icc versus system clock frequency
ps019707-1003 p r e l i m i n a r y electrical characteristics z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 176 stics ac characteristics the section provides information on the ac characteristics and tim ing. all ac timing information assumes a standard load of 50pf on all outputs. figure 39. icc versus system clock frequency table 96. ac characteristics symbol parameter v dd = 2.7 - 3.6v t a = 0 0 c to 70 0 c units conditions minimum maximum f sysclk system clock frequency ? 20.0 mhz read-only from flash memory. 0.032768 20.0 mhz program or erasure of the flash memory. f xtal crystal oscillator frequency 0.032768 20.0 mhz system clock frequencies below the crystal oscillator minimum require an external clock driver. t xin system clock period 50 ? ns t clk = 1/f sysclk t xinh system clock high time 20 30 ns t clk = 50ns
ps019707-1003 p r e l i m i n a r y electrical characteristics z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 177 t xinl system clock low time 20 30 ns t clk = 50ns t xinr system clock rise time ? 3ns t clk = 50ns t xinf system clock fall time ? 3ns t clk = 50ns table 96. ac charact eristics (continued) symbol parameter v dd = 2.7 - 3.6v t a = 0 0 c to 70 0 c units conditions minimum maximum
ps019707-1003 p r e l i m i n a r y electrical characteristics z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 178 on-chip peripheral ac and dc electrical characteristics table 97. power-on reset and voltage brown-out electrical characteristics and timing symbol parameter t a = -40 0 c to 105 0 c units conditions minimum typical 1 maximum v por power-on reset voltage threshold 2.15 2.40 2.60 v v dd = v por v vbo voltage brown-out reset voltage threshold 2.05 2.30 2.55 v v dd = v vbo v por to v vbo hysteresis 50 100 ? mv starting v dd voltage to ensure valid power-on reset. ? v ss ? v t ana power-on reset analog delay ? 50 ? s v dd > v por ; t por digital reset delay follows t ana t por power-on reset digital delay ? 10.2 ? ms 512 wdt oscillator cycles (50khz) + 70 system clock cycles (20mhz) t vbo voltage brown-out pulse rejection period ? 10 ? s v dd < v vbo to generate a reset. t ramp time for vdd to transition from v ss to v por to ensure valid reset 0.10 ? 100 ms 1 data in the typical column is fr om characterization at 3.3v and 0 0 c. these values are prov ided for design guidance only and are not tested in production. table 98. flash memory electrica l characteristics and timing parameter v dd = 2.7 - 3.6v t a = -40 0 c to 105 0 c units notes minimum typical maximum flash byte read time 50 ? ? s flash byte program time 20 ? 40 s flash page erase time 10 ? ? ms flash mass erase time 200 ? ? ms
ps019707-1003 p r e l i m i n a r y electrical characteristics z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 179 writes to single address before next erase ?? 2 flash row program time ? ? 8 ms cumulative program time for single row cannot exceed limit before next erase. this parameter is only an issue when bypassing the flash controller. data retention 100 ? ? years 25 0 c endurance 10,000 ? ? cycles program / erase cycles table 99. watch-dog timer electrical characteristics and timing symbol parameter v dd = 2.7 - 3.6v t a = -40 0 c to 105 0 c units conditions minimum typical maximum f wdt wdt oscillator frequency 51020khz table 100. analog-to-digit al converter electrical ch aracteristics and timing symbol parameter v dd = 2.7 - 3.6v t a = -40 0 c to 105 0 c units conditions minimum typical maximum resolution ? 10 ? bits external v ref = 3.0v; r s <= 3.0 k ? differential nonlinearity (dnl) -1.0 ? 1.0 lsb external v ref = 3.0v; r s <= 3.0 k ? integral nonlinearity (inl) -3.0 ? 3.0 lsb external v ref = 3.0v; r s <= 3.0 k ? dc offset error -35 ? 35 mv 1 analog source impedance affects the adc offset volta ge (because of pin leakage) and input se ttling time. table 98. flash memory electrical char acteristics and timing (continued) parameter v dd = 2.7 - 3.6v t a = -40 0 c to 105 0 c units notes minimum typical maximum
ps019707-1003 p r e l i m i n a r y electrical characteristics z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 180 v ref internal reference voltage 1.8 2.0 2.55 v single-shot conversion time ? 5129 ? cycles system clock cycles continuous conversion time ? 256 ? cycles system clock cycles sampling rate system clock / 256 hz signal input bandwidth ? ? 3.5 khz r s analog source impedance ? ? 10 1 k ? zin input impedance 150 k ? 20mhz system clock. input impedance increases with lower system clock frequency. v ref external reference voltage avdd v avdd <= vdd. when using an external reference voltage, decoupling capacitance should be placed from vref to av s s . i ref current draw into vref pin when driving with external source. 25.0 40.0 a table 100. analog-to-digital co nverter electrical characterist ics and timing (continued) symbol parameter v dd = 2.7 - 3.6v t a = -40 0 c to 105 0 c units conditions minimum typical maximum 1 analog source impedance affects the adc offset volta ge (because of pin leakage) and input se ttling time.
ps019707-1003 p r e l i m i n a r y electrical characteristics z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 181 general purpose i/o port input data sample timing figure 40 illustrates timing of the gpio port input sampling. the in put value on a gpio port pin is sampled on the rising edge of the sy stem clock. the port va lue is then available to the ez8 cpu on the second rising clock e dge following the change of the port value. figure 40. port input sample timing table 101. gpio port input timing parameter abbreviation delay (ns) min max t s_port port input transition to xin rise setup time (not pictured) 5? t h_port xin rise to port input transition hold time (not pictured) 5? t smr gpio port pin pulse width to insure stop mode recovery (for gpio port pins enabled as smr sources) 1 s system tclk port pin port value changes to 0 0 value may be read from port input input value port input data register latch clock data register
ps019707-1003 p r e l i m i n a r y electrical characteristics z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 182 general purpose i/o port output timing figure 41 and table 102 provide timin g information for gpio port pins. figure 41. gpio port output timing table 102. gpio port output timing parameter abbreviation delay (ns) min max gpio port pins t 1 xin rise to port output valid delay ? 15 t 2 xin rise to port output hold time 2 ? xin port output tclk t1 t2
ps019707-1003 p r e l i m i n a r y electrical characteristics z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 183 on-chip debugger timing figure 42 and table 103 provide timing info rmation for the dbg pin. the dbg pin tim- ing specifications assume a 4ns maximum rise and fall time. figure 42. on-chip debugger timing table 103. on-chip debugger timing parameter abbreviation delay (ns) min max dbg t 1 xin rise to dbg valid delay ? 15 t 2 xin rise to dbg output hold time 2 ? t 3 dbg to xin rise input setup time 10 ? t 4 dbg to xin rise input hold time 5 ? xin dbg tclk t1 t2 (output) dbg t3 t4 (input) output data input data
ps019707-1003 p r e l i m i n a r y electrical characteristics z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 184 spi master mode timing figure 43 and table 104 provide timing inform ation for spi master mode pins. timing is shown with sck rising edge used to sour ce mosi output data, sck falling edge used to sample miso input data. timing on the ss output pin(s) is controlled by software. figure 43. spi master mode timing table 104. spi master mode timing parameter abbreviation delay (ns) min max spi master t 1 sck rise to mosi output valid delay -5 +5 t 2 miso input to sck (recei ve edge) setup time 20 t 3 miso input to sck (recei ve edge) hold time 0 sck mosi t1 (output) miso t2 t3 (input) output data input data
ps019707-1003 p r e l i m i n a r y electrical characteristics z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 185 spi slave mode timing figure 44 and table 105 provide timing info rmation for the spi sla ve mode pins. tim- ing is shown with sck rising edge used to source miso output data, sck falling edge used to sample mosi input data. figure 44. spi slave mode timing table 105. spi slave mode timing parameter abbreviation delay (ns) min max spi slave t 1 sck (transmit edge) to miso output valid delay 2 * xin period 3 * xin period + 20 nsec t 2 mosi input to sck (receive edge) setup time 0 t 3 mosi input to sck (receive edge) hold time 3 * xin period t 4 ss input assertion to sck setup 1 * xin period sck miso t1 (output) mosi t2 t3 (input) output data input data ss (input) t4
ps019707-1003 p r e l i m i n a r y electrical characteristics z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 186 i 2 c timing figure 45 and table 106 prov ide timing information for i 2 c pins. figure 45. i 2 c timing table 106. i 2 c timing parameter abbreviation delay (ns) minimum maximum i 2 c t 1 scl fall to sda output delay scl period/4 t 2 sda input to scl rising edge setup time 0 t 3 sda input to scl falling edge hold time 0 scl sda t1 (output) sda t2 (input) output data input data (output) t3
ps019707-1003 p r e l i m i n a r y electrical characteristics z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 187 uart timing figure 46 and table 107 provide timing info rmation for uart pins for the case where cts is used for flow control. the cts to de assertion delay (t1) assumes the transmit data register has been loaded with data prior to cts assertion. figure 46. uart timing with cts figure 47 and table 108 provide timing info rmation for uart pins for the case where cts is not used for flow contro l. de asserts after the transmit data register has been writ- ten. de remains asserted for mu ltiple characters as long as the transmit data register is written with the next character before the current character has completed. table 107. uart timing with cts parameter abbreviation delay (ns) minimum maximum uart t 1 cts fall to de output delay 2 * xin period 2 * xin period + 1 bit time t 2 de assertion to txd falling edge (start bit) delay +/- 5 t 3 end of stop bit(s) to de deassertion delay +/- 5 cts de t1 (output) txd t2 (output) (input) start bit0 bit bit7 parity stop end of stop bit(s) t3
ps019707-1003 p r e l i m i n a r y electrical characteristics z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 188 figure 47. uart timing without cts table 108. uart timing without cts parameter abbreviation delay (ns) minimum maximum uart t 1 de assertion to txd falling edge (start bit) delay 1 * xin period 1 bit time t 2 end of stop bit(s) to de deassertion delay (tx data register is empty) +/- 5 de t1 (output) txd t2 (output) start bit0 bit1 bit7 parity stop end of stop bit(s)
z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? ps019707-1003 p r e l i m i n a r y ez8 cpu instruction set 188 ez8 cpu instruction set assembly language pro gramming introduction the ez8 cpu assembly language provides a me ans for writing an application program without having to be concerned with actual memory addresses or machine instruction for- mats. a program written in assembly language is called a source program. assembly lan- guage allows the use of symbolic addresses to identify memory locations. it also allows mnemonic codes (opcodes and operands) to re present the instructio ns themselves. the opcodes identify the in struction while the operands represe nt memory locations, registers, or immediate data values. each assembly language program consists of a series of symbolic commands called state- ments. each statement can contain labe ls, operations, operands and comments. labels can be assigned to a particular instru ction step in a source program. the label iden- tifies that step in the program as an entry point for use by other instructions. the assembly language also includes assembl er directives that supplement the machine instruction. the assembler directives, or p seudo-ops, are not transl ated into a machine instruction. rather, the pseudo-ops are interp reted as directives that control or assist the assembly process. the source program is processed (assembled) by the assembler to obtain a machine lan- guage program called the object code. the object code is executed by the ez8 cpu. an example segment of an assembly language pr ogram is detailed in the following example. assembly language source program example jp start ; everything after the semicolon is a comment. start: ; a label called ?start?. the first instruction ( jp start ) in this ; example causes program execution to jump to the point within the ; program where the start label occurs. ld r4, r7 ; a load (ld) instruction with two operands. the first operand, ; working register r4, is the de stination. the second operand, ; working register r7, is the so urce. the contents of r7 is ; written into r4. ld 234h, #%01 ; another load (ld) instruction with two operands. ; the first operand, extended mode register address 234h , ; identifies the destination. the second operand, immediate data
ps019707-1003 p r e l i m i n a r y ez8 cpu instruction set z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 189 ; value 01h , is the source. the value 01h is written into the ; register at address 234h . assembly language syntax for proper instruction execution, ez8 cpu ass embly language syntax requires that the operands be written as ?destination, source?. af ter assembly, the obj ect code usually has the operands in the order ?source, destination? , but ordering is opcode-dependent. the fol- lowing instruction examples illust rate the format of some ba sic assembly instructions and the resulting object code produced by the assembler. this binary format must be followed by users that prefer manual program coding or intend to implement their own assembler. example 1 : if the contents of registers 43h and 08h are added and the result is stored in 43h, the assembly syntax and resulting object code is: example 2 : in general, when an instruction format requires an 8-bit register address, that address can specify any regist er location in the range 0 - 255 or, using escaped mode addressing, a working register r0 - r15. if the contents of register 43h and working register r8 are added and the result is stor ed in 43h, the assembl y syntax and resulting object code is: see the device-specific product specification to determine the exact register file range available. the register file size va ries, depending on the device type. ez8 cpu instruction notation in the ez8 cpu instruction summary and description sections, th e operands, condition codes, status flags, and addr ess modes are represented by a notational shorthand that is described in table 111 table 109. assembly language syntax example 1 assembly language code add 43h 08h (add dst, src) object code 04 08 43 (opc src, dst) table 110. assembly language syntax example 2 assembly language code add 43h, r8 (add dst, src) object code 04 e8 43 (opc src, dst)
ps019707-1003 p r e l i m i n a r y ez8 cpu instruction set z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 190 . table 112 contains additional symbols that ar e used throughout th e instruction summary and instruction set description sections. table 111. notational shorthand notation description operand range b bit b b represents a value from 0 to 7 (000b to 111b). cc condition code ? see condition codes overview in the ez8 cpu user manual. da direct address addrs addrs. represents a number in the range of 0000h to ffffh er extended addressing register reg reg. represents a number in the range of 000h to fffh im immediate data #data data is a number between 00h to ffh ir indirect working register @rn n = 0 ?15 ir indirect register @reg reg. represents a number in the range of 00h to ffh irr indirect working register pair @rrp p = 0, 2, 4, 6, 8, 10, 12, or 14 irr indirect register pair @reg reg. represen ts an even number in the range 00h to feh p polarity p polarity is a single bit binary value of either 0b or 1b. r working register rn n = 0 ? 15 r register reg reg. represents a numb er in the range of 00h to ffh ra relative address x x represents an index in the range of +127 to ?128 which is an offset relative to the address of the next instruction rr working register pair rrp p = 0, 2, 4, 6, 8, 10, 12, or 14 rr register pair reg reg. represents an even number in the range of 00h to feh vector vector address vector vector represen ts a number in the range of 00h to ffh x indexed #index the register or register pair to be indexed is offset by the signed index value (#index) in a +127 to -128 range.
ps019707-1003 p r e l i m i n a r y ez8 cpu instruction set z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 191 assignment of a value is indicated by an arrow. for example, dst dst + src indicates the source data is added to the destin ation data and the result is stored in the des- tination location. table 112. additional symbols symbol definition dst destination operand src source operand @ indirect address prefix sp stack pointer pc program counter flags flags register rp register pointer # immediate operand prefix b binary number suffix % hexadecimal number prefix h hexadecimal number suffix
ps019707-1003 p r e l i m i n a r y ez8 cpu instruction set z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 192 condition codes the c, z, s and v flags control the operatio n of the conditional jump (jp cc and jr cc) instructions. sixteen frequently useful functions of the flag settings are encoded in a 4-bit field called the condition code (cc), which form s bits 7:4 of the conditional jump instruc- tions. the condition codes are su mmarized in table 113. some binary condition codes can be created using more than one assembly code mnemonic. the result of the flag test oper- ation decides if the cond itional jump is executed. table 113. condition codes binary hex assembly mnemonic definition flag test operation 0000 0 f always false ? 0001 1 lt less than (s xor v) = 1 0010 2 le less than or equal (z or (s xor v)) = 1 0011 3 ule unsigned less than or equal (c or z) = 1 0100 4 ov overflow v = 1 0101 5 ml minus s = 1 0110 6 z zero z = 1 0110 6 eq equal z = 1 0111 7 c carry c = 1 0111 7 ult unsigned less than c = 1 1000 8 t (or blank) always true ? 1001 9 ge greater than or equal (s xor v) = 0 1010 a gt greater than (z or (s xor v)) = 0 1011 b ugt unsigned greater than (c = 0 and z = 0) = 1 1100 c nov no overflow v = 0 1101 d pl plus s = 0 1110 e nz non-zero z = 0 1110 e ne not equal z = 0 1111 f nc no carry c = 0 1111 f uge unsigned greater than or equal c = 0
ps019707-1003 p r e l i m i n a r y ez8 cpu instruction set z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 193 ez8 cpu instruction classes ez8 cpu instructions can be divided fu nctionally into the following groups: ? arithmetic ? bit manipulation ? block transfer ? cpu control ? load ? logical ? program control ? rotate and shift tables 114 through 121 contain the instructions belonging to each group and the number of operands required for each instruction. some inst ructions appear in more than one table as these instruction can be considered as a subs et of more than one category. within these tables, the source operand is identified as ?s rc?, the destination op erand is ?dst? and a con- dition code is ?cc?. table 114. arithmetic instructions mnemonic operands instruction adc dst, src add with carry adcx dst, src add with carry using extended addressing add dst, src add addx dst, src add using extended addressing cp dst, src compare cpc dst, src compare with carry cpcx dst, src compare with carry using extended addressing cpx dst, src compare using extended addressing da dst decimal adjust dec dst decrement decw dst decrement word inc dst increment incw dst increment word mult dst multiply
ps019707-1003 p r e l i m i n a r y ez8 cpu instruction set z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 194 sbc dst, src subtract with carry sbcx dst, src subtract with carry using extended addressing sub dst, src subtract subx dst, src subtract using extended addressing table 115. bit manipulation instructions mnemonic operands instruction bclr bit, dst bit clear bit p, bit, dst bit set or clear bset bit, dst bit set bswap dst bit swap ccf ? complement carry flag rcf ? reset carry flag scf ? set carry flag tcm dst, src test complement under mask tcmx dst, src test complement under mask using extended addressing tm dst, src test under mask tmx dst, src test under mask using extended addressing table 116. block transfer instructions mnemonic operands instruction ldci dst, src load constant to/from program memory and auto-increment addresses ldei dst, src load external data to/from data memory and auto-increment addresses table 114. arithmetic in structions (continued) mnemonic operands instruction
ps019707-1003 p r e l i m i n a r y ez8 cpu instruction set z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 195 table 117. cpu control instructions mnemonic operands instruction ccf ? complement carry flag di ? disable interrupts ei ? enable interrupts halt ? halt mode nop ? no operation rcf ? reset carry flag scf ? set carry flag srp src set register pointer stop ? stop mode wdt ? watch-dog timer refresh table 118. load instructions mnemonic operands instruction clr dst clear ld dst, src load ldc dst, src load constant to/from program memory ldci dst, src load constant to/from program memory and auto-increment addresses lde dst, src load external data to/from data memory ldei dst, src load external data to/from data memory and auto-increment addresses ldx dst, src load using extended addressing lea dst, x(src) load effective address pop dst pop popx dst pop using extended addressing push src push pushx src push using extended addressing
ps019707-1003 p r e l i m i n a r y ez8 cpu instruction set z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 196 table 119. logical instructions mnemonic operands instruction and dst, src logical and andx dst, src logical and using extended addressing com dst complement or dst, src logical or orx dst, src logical or using extended addressing xor dst, src logical exclusive or xorx dst, src logical exclusive or using extended addressing table 120. program control instructions mnemonic operands instruction brk ? on-chip debugger break btj p, bit, src, da bit test and jump btjnz bit, src, da bit test and jump if non-zero btjz bit, src, da bit test and jump if zero call dst call procedure djnz dst, src, ra decr ement and jump non-zero iret ? interrupt return jp dst jump jp cc dst jump conditional jr da jump relative jr cc da jump relative conditional ret ? return trap vector software trap
ps019707-1003 p r e l i m i n a r y ez8 cpu instruction set z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 197 ez8 cpu instruction summary table 122 summarizes the ez8 cpu instruc tions. the table identifies the addressing modes employed by the instruction, the effect upon the flags register, the number of cpu clock cycles required for th e instruction fetch, and the number of cpu clock cycles required for the instruction execution. . table 121. rotate and shift instructions mnemonic operands instruction bswap dst bit swap rl dst rotate left rlc dst rotate left through carry rr dst rotate right rrc dst rotate right through carry sra dst shift right arithmetic srl dst shift right logical swap dst swap nibbles table 122. ez8 cpu instruction summary assembly mnemonic symbol ic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h adc dst, src dst dst + src + c r r 12 ****0* 2 3 rir 13 24 rr 14 33 rir 15 3 4 rim 16 3 3 ir im 17 3 4 adcx dst, src dst dst + src + c er er 18 ****0* 4 3 er im 19 4 3 flags notation: * = value is a function of the result of the operation. - = unaffected x = undefined 0 = reset to 0 1 = set to 1
ps019707-1003 p r e l i m i n a r y ez8 cpu instruction set z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 198 add dst, src dst dst + src r r 02 ****0* 2 3 rir 03 24 rr 04 33 rir 05 3 4 rim 06 3 3 ir im 07 3 4 addx dst, src dst dst + src er er 08 ****0* 4 3 er im 09 4 3 and dst, src dst dst and src r r 52 - * * 0 - - 2 3 rir 53 24 rr 54 33 rir 55 3 4 rim 56 3 3 ir im 57 3 4 andx dst, src dst dst and src er er 58 - * * 0 - - 4 3 er im 59 4 3 bclr bit, dst dst[bit] 0re2-**0--22 bit p, bit, dst dst[bit] pre2-**0--22 brk debugger break 00 - - - - - - 1 1 bset bit, dst dst[bit] 1re2-**0--22 bswap dst dst[7:0] dst[0:7] r d5 x * * 0 - - 2 2 btj p, bit, src, dst if src[bit] = p pc pc + x r f6 ------ 3 3 ir f7 3 4 btjnz bit, src, dst if src[bit] = 1 pc pc + x r f6 ------ 3 3 ir f7 3 4 table 122. ez8 cpu instruct ion summary (continued) assembly mnemonic symbol ic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h flags notation: * = value is a function of the result of the operation. - = unaffected x = undefined 0 = reset to 0 1 = set to 1
ps019707-1003 p r e l i m i n a r y ez8 cpu instruction set z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 199 btjz bit, src, dst if src[bit] = 0 pc pc + x r f6 ------ 3 3 ir f7 3 4 call dst sp sp -2 @sp pc pc dst irr d4 ------ 2 6 da d6 3 3 ccf c ~c ef *----- 1 2 clr dst dst 00h r b0 ------ 2 2 ir b1 2 3 com dst dst ~dst r 60 - * * 0 - - 2 2 ir 61 2 3 cp dst, src dst - src r r a2 * * * * - - 2 3 rir a3 24 rr a4 33 rir a5 3 4 rim a6 3 3 ir im a7 3 4 cpc dst, src dst - src - c r r 1f a2 * * * * - - 3 3 rir1f a3 34 rr1f a4 43 rir1f a5 4 4 rim1f a6 4 3 ir im 1f a7 4 4 cpcx dst, src dst - src - c er er 1f a8 * * * * - - 5 3 er im 1f a9 5 3 cpx dst, src dst - src er er a8 * * * * - - 4 3 er im a9 4 3 table 122. ez8 cpu instruct ion summary (continued) assembly mnemonic symbol ic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h flags notation: * = value is a function of the result of the operation. - = unaffected x = undefined 0 = reset to 0 1 = set to 1
ps019707-1003 p r e l i m i n a r y ez8 cpu instruction set z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 200 da dst dst da(dst) r 40 * * * x - - 2 2 ir 41 2 3 dec dst dst dst - 1 r 30 - * * * - - 2 2 ir 31 2 3 decw dst dst dst - 1 rr 80 - * * * - - 2 5 irr 81 2 6 di irqctl[7] 0 8f ------ 1 2 djnz dst, ra dst dst ? 1 if dst 0 pc pc + x r 0a-fa ------ 2 3 ei irqctl[7] 1 9f ------ 1 2 halt halt mode 7f ------ 1 2 inc dst dst dst + 1 r 20 - * * * - - 2 2 ir 21 2 3 r0e-fe 12 incw dst dst dst + 1 rr a0 - * * * - - 2 5 irr a1 2 6 iret flags @sp sp sp + 1 pc @sp sp sp + 2 irqctl[7] 1 bf ****** 1 5 jp dst pc dst da 8d ------ 3 2 irr c4 2 3 jp cc, dst if cc is true pc dst da 0d-fd ------ 3 2 jr dst pc pc + x da 8b ------ 2 2 jr cc, dst if cc is true pc pc + x da 0b-fb ------ 2 2 table 122. ez8 cpu instruct ion summary (continued) assembly mnemonic symbol ic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h flags notation: * = value is a function of the result of the operation. - = unaffected x = undefined 0 = reset to 0 1 = set to 1
ps019707-1003 p r e l i m i n a r y ez8 cpu instruction set z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 201 ld dst, rc dst src r im 0c-fc ------ 2 2 rx(r) c7 3 3 x(r) r d7 3 4 rir e3 23 rr e4 32 rir e5 3 4 rim e6 3 2 ir im e7 3 3 ir r f3 2 3 ir r f5 3 3 ldc dst, src dst src r irr c2 ------ 2 5 ir irr c5 2 9 irr r d2 2 5 ldci dst, src dst src r r + 1 rr rr + 1 ir irr c3 - - - - - - 2 9 irr ir d3 2 9 lde dst, src dst src r irr 82 ------ 2 5 irr r 92 2 5 ldei dst, src dst src r r + 1 rr rr + 1 ir irr 83 - - - - - - 2 9 irr ir 93 2 9 table 122. ez8 cpu instruct ion summary (continued) assembly mnemonic symbol ic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h flags notation: * = value is a function of the result of the operation. - = unaffected x = undefined 0 = reset to 0 1 = set to 1
ps019707-1003 p r e l i m i n a r y ez8 cpu instruction set z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 202 ldx dst, src dst src r er 84 ------ 3 2 ir er 85 3 3 rirr 86 3 4 ir irr 87 3 5 r x(rr) 88 3 4 x(rr) r 89 3 4 er r 94 3 2 er ir 95 3 3 irr r 96 3 4 irr ir 97 3 5 er er e8 4 2 er im e9 4 2 lea dst, x(src) dst src + x r x(r) 98 ------ 3 3 rr x(rr) 99 3 5 mult dst dst[15:0] dst[15:8] * dst[7:0] rr f4 ------ 2 8 nop no operation 0f - - - - - - 1 2 or dst, src dst dst or src r r 42 - * * 0 - - 2 3 rir 43 24 rr 44 33 rir 45 3 4 rim 46 3 3 ir im 47 3 4 orx dst, src dst dst or src er er 48 - * * 0 - - 4 3 er im 49 4 3 table 122. ez8 cpu instruct ion summary (continued) assembly mnemonic symbol ic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h flags notation: * = value is a function of the result of the operation. - = unaffected x = undefined 0 = reset to 0 1 = set to 1
ps019707-1003 p r e l i m i n a r y ez8 cpu instruction set z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 203 pop dst dst @sp sp sp + 1 r 50 ------ 2 2 ir 51 2 3 popx dst dst @sp sp sp + 1 er d8 ------ 3 2 push src sp sp ? 1 @sp src r 70 ------ 2 2 ir 71 2 3 pushx src sp sp ? 1 @sp src er c8 ------ 3 2 rcf c 0 cf 0----- 1 2 ret pc @sp sp sp + 2 af ------ 1 4 rl dst r 90 * * * * - - 2 2 ir 91 2 3 rlc dst r 10 * * * * - - 2 2 ir 11 2 3 rr dst r e0 ****- - 2 2 ir e1 2 3 rrc dst r c0 * * * * - - 2 2 ir c1 2 3 table 122. ez8 cpu instruct ion summary (continued) assembly mnemonic symbol ic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h flags notation: * = value is a function of the result of the operation. - = unaffected x = undefined 0 = reset to 0 1 = set to 1 d7 d6 d5 d4 d3 d2 d1 d0 dst c d7 d6 d5 d4 d3 d2 d1 d0 dst c d7 d6 d5 d4 d3 d2 d1 d0 dst c d7 d6 d5 d4 d3 d2 d1 d0 dst c
ps019707-1003 p r e l i m i n a r y ez8 cpu instruction set z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 204 sbc dst, src dst dst ? src - c r r 32 ****1* 2 3 rir 33 24 rr 34 33 rir 35 3 4 rim 36 3 3 ir im 37 3 4 sbcx dst, src dst dst ? src - c er er 38 ****1* 4 3 er im 39 4 3 scf c 1 df 1----- 1 2 sra dst r d0 ***0- - 2 2 ir d1 2 3 srl dst r 1f c0 **0*- - 3 2 ir 1f c1 3 3 srp src rp src im 01 ------ 2 2 stop stop mode 6f ------ 1 2 sub dst, src dst dst ? src r r 22 ****1* 2 3 rir 23 24 rr 24 33 rir 25 3 4 rim 26 3 3 ir im 27 3 4 subx dst, src dst dst ? src er er 28 ****1* 4 3 er im 29 4 3 swap dst dst[7:4] ? dst[3:0] r f0 x * * x - - 2 2 ir f1 2 3 table 122. ez8 cpu instruct ion summary (continued) assembly mnemonic symbol ic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h flags notation: * = value is a function of the result of the operation. - = unaffected x = undefined 0 = reset to 0 1 = set to 1 d7 d6 d5 d4 d3 d2 d1 d0 dst c d7 d6 d5 d4 d3 d2 d1 d0 dst c 0
ps019707-1003 p r e l i m i n a r y ez8 cpu instruction set z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 205 tcm dst, src (not dst) and src r r 62 - * * 0 - - 2 3 rir 63 24 rr 64 33 rir 65 3 4 rim 66 3 3 ir im 67 3 4 tcmx dst, src (not dst) and src er er 68 - * * 0 - - 4 3 er im 69 4 3 tm dst, src dst and src r r 72 - * * 0 - - 2 3 rir 73 24 rr 74 33 rir 75 3 4 rim 76 3 3 ir im 77 3 4 tmx dst, src dst and src er er 78 - * * 0 - - 4 3 er im 79 4 3 trap vector sp sp ? 2 @sp pc sp sp ? 1 @sp flags pc @vector vector f2 ------ 2 6 wdt 5f ------ 1 2 table 122. ez8 cpu instruct ion summary (continued) assembly mnemonic symbol ic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h flags notation: * = value is a function of the result of the operation. - = unaffected x = undefined 0 = reset to 0 1 = set to 1
ps019707-1003 p r e l i m i n a r y ez8 cpu instruction set z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 206 xor dst, src dst dst xor src r r b2 - * * 0 - - 2 3 rir b3 24 rr b4 33 rir b5 3 4 rim b6 3 3 ir im b7 3 4 xorx dst, src dst dst xor src er er b8 - * * 0 - - 4 3 er im b9 4 3 table 122. ez8 cpu instruct ion summary (continued) assembly mnemonic symbol ic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h flags notation: * = value is a function of the result of the operation. - = unaffected x = undefined 0 = reset to 0 1 = set to 1
ps019707-1003 p r e l i m i n a r y ez8 cpu instruction set z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 207 flags register the flags register contains the status inform ation regarding the most recent arithmetic, logical, bit manipulation or rotate and shift oper ation. the flags register contains six bits of status information that are set or cleared by cpu operations. four of the bits (c, v, z and s) can be tested with conditional jump in structions. two flags (h and d) cannot be tested and are used for binary -coded decimal (bcd) arithmetic. the two remaining bits, user flags (f1 and f2 ), are available as general-purpose status bits. user flags are unaffected by arithmetic operations and must be set or cleared by instructions. the user flags cannot be used with conditional jumps. they are undefined at initial power-up and are unaffected by reset. figure 48 illustrates th e flags and their bit positions in the flags register. figure 48. flags register interrupts, the software trap (trap) instruction, and illegal instruction traps all write the value of the flags register to the stack. executing an interrupt return (iret) instruc- tion restores the value saved on th e stack into the flags register. c z s v d h f2 f1 flags register bit 0 bit 7 half carry flag decimal adjust flag overflow flag sign flag zero flag carry flag user flags
z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? ps019707-1003 p r e l i m i n a r y opcode maps 208 opcode maps figures 50 and 51 provide information on each of the ez8 cpu instructions. a description of the opcode map data and the abbreviations are provided in figure 49 and table 123. figure 49. opcode map cell description cp 3.3 r2,r1 a 4 opcode lower nibble second operand after assembly first operand after assembly opcode upper nibble instruction cycles fetch cycles
ps019707-1003 p r e l i m i n a r y opcode maps z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 209 table 123. opcode map abbreviations abbreviation description a bbreviation description b bit position irr indirect register pair cc condition code p polarity (0 or 1) x 8-bit signed index or displacement r 4-bit working register da destination address r 8-bit register er extended addressing register r1, r1, ir1, irr1, ir1, rr1, rr1, irr1, er1 destination address im immediate data value r2, r2, ir2, irr2, ir2, rr2, rr2, irr2, er2 source address ir indirect working register ra relative ir indirect register rr working register pair irr indirect working register pair rr register pair
ps019707-1003 p r e l i m i n a r y opcode maps z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 210 figure 50. first opcode map cp 3.3 r2,r1 cp 3.4 ir2,r1 cp 2.3 r1,r2 cp 2.4 r1,ir2 cpx 4.3 er2,er1 cpx 4.3 im,er1 cp 3.3 r1,im cp 3.4 ir1,im rrc 2.2 r1 rrc 2.3 ir1 0 1 2 3 4 5 6 7 8 9abcde f 0 1 2 3 4 5 6 7 8 9 a b c d e f lower nibble (hex) upper nibble (hex) brk 1.2 srp 2.2 im add 2.3 r1,r2 add 2.4 r1,ir2 add 3.3 r2,r1 add 3.4 ir2,r1 add 3.3 r1,im add 3.4 ir1,im addx 4.3 er2,er1 addx 4.3 im,er1 djnz 2.3 r1,x jr 2.2 cc,x ld 2.2 r1,im jp 3.2 cc,da inc 1.2 r1 nop 1.2 rlc 2.2 r1 rlc 2.3 ir1 adc 2.3 r1,r2 adc 2.4 r1,ir2 adc 3.3 r2,r1 adc 3.4 ir2,r1 adc 3.3 r1,im adc 3.4 ir1,im adcx 4.3 er2,er1 adcx 4.3 im,er1 inc 2.2 r1 inc 2.3 ir1 sub 2.3 r1,r2 sub 2.4 r1,ir2 sub 3.3 r2,r1 sub 3.4 ir2,r1 sub 3.3 r1,im sub 3.4 ir1,im subx 4.3 er2,er1 subx 4.3 im,er1 dec 2.2 r1 dec 2.3 ir1 sbc 2.3 r1,r2 sbc 2.4 r1,ir2 sbc 3.3 r2,r1 sbc 3.4 ir2,r1 sbc 3.3 r1,im sbc 3.4 ir1,im sbcx 4.3 er2,er1 sbcx 4.3 im,er1 da 2.2 r1 da 2.3 ir1 or 2.3 r1,r2 or 2.4 r1,ir2 or 3.3 r2,r1 or 3.4 ir2,r1 or 3.3 r1,im or 3.4 ir1,im orx 4.3 er2,er1 orx 4.3 im,er1 pop 2.2 r1 pop 2.3 ir1 and 2.3 r1,r2 and 2.4 r1,ir2 and 3.3 r2,r1 and 3.4 ir2,r1 and 3.3 r1,im and 3.4 ir1,im andx 4.3 er2,er1 andx 4.3 im,er1 com 2.2 r1 com 2.3 ir1 tcm 2.3 r1,r2 tcm 2.4 r1,ir2 tcm 3.3 r2,r1 tcm 3.4 ir2,r1 tcm 3.3 r1,im tcm 3.4 ir1,im tcmx 4.3 er2,er1 tcmx 4.3 im,er1 push 2.2 r2 push 2.3 ir2 tm 2.3 r1,r2 tm 2.4 r1,ir2 tm 3.3 r2,r1 tm 3.4 ir2,r1 tm 3.3 r1,im tm 3.4 ir1,im tmx 4.3 er2,er1 tmx 4.3 im,er1 decw 2.5 rr1 decw 2.6 irr1 lde 2.5 r1,irr2 ldei 2.9 ir1,irr2 ldx 3.2 r1,er2 ldx 3.3 ir1,er2 ldx 3.4 irr2,r1 ldx 3.5 irr2,ir1 ldx 3.4 r1,rr2,x ldx 3.4 rr1,r2,x rl 2.2 r1 rl 2.3 ir1 lde 2.5 r2,irr1 ldei 2.9 ir2,irr1 ldx 3.2 r2,er1 ldx 3.3 ir2,er1 ldx 3.4 r2,irr1 ldx 3.5 ir2,irr1 lea 3.3 r1,r2,x lea 3.5 rr1,rr2,x incw 2.5 rr1 incw 2.6 irr1 clr 2.2 r1 clr 2.3 ir1 xor 2.3 r1,r2 xor 2.4 r1,ir2 xor 3.3 r2,r1 xor 3.4 ir2,r1 xor 3.3 r1,im xor 3.4 ir1,im xorx 4.3 er2,er1 xorx 4.3 im,er1 ldc 2.5 r1,irr2 ldci 2.9 ir1,irr2 ldc 2.5 r2,irr1 ldci 2.9 ir2,irr1 jp 2.3 irr1 ldc 2.9 ir1,irr2 ld 3.4 r1,r2,x pushx 3.2 er2 sra 2.2 r1 sra 2.3 ir1 popx 3.2 er1 ld 3.4 r2,r1,x call 2.6 irr1 bswap 2.2 r1 call 3.3 da ld 3.2 r2,r1 ld 3.3 ir2,r1 bit 2.2 p,b,r1 ld 2.3 r1,ir2 ldx 4.2 er2,er1 ldx 4.2 im,er1 ld 3.2 r1,im ld 3.3 ir1,im rr 2.2 r1 rr 2.3 ir1 mult 2.8 rr1 ld 3.3 r2,ir1 trap 2.6 vector ld 2.3 ir1,r2 btj 3.3 p,b,r1,x btj 3.4 p,b,ir1,x swap 2.2 r1 swap 2.3 ir1 rcf 1.2 wdt 1.2 stop 1.2 halt 1.2 di 1.2 ei 1.2 ret 1.4 iret 1.5 scf 1.2 ccf 1.2 opcode see 2nd map
ps019707-1003 p r e l i m i n a r y opcode maps z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 211 figure 51. second op code map after 1fh cpc 4.3 r2,r1 cpc 4.4 ir2,r1 cpc 3.3 r1,r2 cpc 3.4 r1,ir2 cpcx 5.3 er2,er1 cpcx 5.3 im,er1 cpc 4.3 r1,im cpc 4.4 ir1,im srl 3.2 r1 srl 3.3 ir1 0 1 2 3 4 5 6 7 8 9 a b c d e f 0 1 2 3 4 5 6 7 8 9 a b c d e f lower nibble (hex) upper nibble (hex)
z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? ps019707-1003 p r e l i m i n a r y packaging 212 packaging figure 52 illustrates the 20-pin ssop pack age available for the z8f0411, z8f0421, Z8F0811, and z8f0821 devices. figure 52. 20-pin small shri nk outline package (ssop)
z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? ps019707-1003 p r e l i m i n a r y packaging 213 figure 53 illustrates the 20-pin pdip pack age available for the z8f0411, z8f0421, Z8F0811, and z8f0821 devices. figure 53. 20-pin plastic dual-inline package (pdip)
z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? ps019707-1003 p r e l i m i n a r y packaging 214 figure 54 illustrates the 28-pin soic pack age available for the z8f0412, z8f0422, z8f0812, and z8f0822 devices. figure 54. 28-pin small outline in tegrated circuit package (soic)
z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? ps019707-1003 p r e l i m i n a r y packaging 215 figure 55 illustrates the 28-pin pdip pack age available for the z8f0412, z8f0422, z8f0812, and z8f0822 devices. figure 55. 28-pin plastic dual-inline package (pdip)
z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? ps019707-1003 p r e l i m i n a r y ordering information 216 ordering information table 124. ordering information part flash kb (bytes) ram kb (bytes) max. speed (mhz) temp ( 0 c) voltage (v) package part number z8 encore! ? with 8kb flash and 10-bit analog-t o-digital converter (s tandard temperature) z8 encore! ? 8 (8192) 1 (1024) 20 0 to +70 2.7 - 3.6 ssop-20 z8f0821hh020sc z8 encore! ? 8 (8192) 1 (1024) 20 0 to +70 2.7 - 3.6 pdip-20 z8f0821ph020sc z8 encore! ? 8 (8192) 1 (1024) 20 0 to +70 2.7 - 3.6 soic-28 z8f0822sj020sc z8 encore! ? 8 (8192) 1 (1024) 20 0 to +70 2.7 - 3.6 pdip-28 z8f0822pj020sc z8 encore! ? with 8kb flash and 10-bit analog-t o-digital converter (extended temperature) z8 encore! ? 8 (8192) 1 (1024) 20 -40 to +105 2.7 - 3.6 ssop-20 z8f0821hh020ec z8 encore! ? 8 (8192) 1 (1024) 20 -40 to +105 2.7 - 3.6 pdip-20 z8f0821ph020ec z8 encore! ? 8 (8192) 1 (1024) 20 -40 to +105 2.7 - 3.6 soic-28 z8f0822sj020ec z8 encore! ? 8 (8192) 1 (1024) 20 -40 to +105 2.7 - 3.6 pdip-28 z8f0822pj020ec z8 encore! ? with 8kb flash (standard temperature) z8 encore! ? 8 (8192) 1 (1024) 20 0 to +70 2.7 - 3.6 ssop-20 Z8F0811hh020sc z8 encore! ? 8 (8192) 1 (1024) 20 0 to +70 2.7 - 3.6 pdip-20 Z8F0811ph020sc z8 encore! ? 8 (8192) 1 (1024) 20 0 to +70 2.7 - 3.6 soic-28 z8f0812sj020sc z8 encore! ? 8 (8192) 1 (1024) 20 0 to +70 2.7 - 3.6 pdip-28 z8f0812pj020sc z8 encore! ? with 8kb flash (extended temperature) z8 encore! ? 8 (8192) 1 (1024) 20 -40 to +105 2.7 - 3.6 ssop-20 Z8F0811hh020ec z8 encore! ? 8 (8192) 1 (1024) 20 -40 to +105 2.7 - 3.6 pdip-20 Z8F0811ph020ec z8 encore! ? 8 (8192) 1 (1024) 20 -40 to +105 2.7 - 3.6 soic-28 z8f0812sj020ec z8 encore! ? 8 (8192) 1 (1024) 20 -40 to +105 2.7 - 3.6 pdip-28 z8f0812pj020ec
z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? ps019707-1003 p r e l i m i n a r y ordering information 217 for valuable informa tion about customer and technical support as well as hardware and software development tools, visit the zilog web site at www.zilog.com . the latest released version of zds can be downloaded from this site. z8 encore! ? with 4kb flash and 10-bit analog-t o-digital converter (s tandard temperature) z8 encore! ? 4 (4096) 1 (1024) 20 0 to +70 2.7 - 3.6 ssop-20 z8f0421hh020sc z8 encore! ? 4 (4096) 1 (1024) 20 0 to +70 2.7 - 3.6 pdip-20 z8f0421ph020sc z8 encore! ? 4 (4096) 1 (1024) 20 0 to +70 2.7 - 3.6 soic-28 z8f0422sj020sc z8 encore! ? 4 (4096) 1 (1024) 20 0 to +70 2.7 - 3.6 pdip-28 z8f0422pj020sc z8 encore! ? with 4kb flash and 10-bit analog-t o-digital converter (extended temperature) z8 encore! ? 4 (4096) 1 (1024) 20 -40 to +105 2.7 - 3.6 ssop-20 z8f0421hh020ec z8 encore! ? 4 (4096) 1 (1024) 20 -40 to +105 2.7 - 3.6 pdip-20 z8f0421ph020ec z8 encore! ? 4 (4096) 1 (1024) 20 -40 to +105 2.7 - 3.6 soic-28 z8f0422sj020ec z8 encore! ? 4 (4096) 1 (1024) 20 -40 to +105 2.7 - 3.6 pdip-28 z8f0422pj020ec z8 encore! ? with 4kb flash (standard temperature) z8 encore! ? 4 (4096) 1 (1024) 20 0 to +70 2.7 - 3.6 ssop-20 z8f0411hh020sc z8 encore! ? 4 (4096) 1 (1024) 20 0 to +70 2.7 - 3.6 pdip-20 z8f0411ph020sc z8 encore! ? 4 (4096) 1 (1024) 20 0 to +70 2.7 - 3.6 soic-28 z8f0412sj020sc z8 encore! ? 4 (4096) 1 (1024) 20 0 to +70 2.7 - 3.6 pdip-28 z8f0412pj020sc z8 encore! ? with 4kb flash (extended temperature) z8 encore! ? 4 (4096) 1 (1024) 20 -40 to +105 2.7 - 3.6 ssop-20 z8f0411hh020ec z8 encore! ? 4 (4096) 1 (1024) 20 -40 to +105 2.7 - 3.6 pdip-20 z8f0411ph020ec z8 encore! ? 4 (4096) 1 (1024) 20 -40 to +105 2.7 - 3.6 soic-28 z8f0412sj020ec z8 encore! ? 4 (4096) 1 (1024) 20 -40 to +105 2.7 - 3.6 pdip-28 z8f0412pk020ec z8 encore! ? evaluation kit z8f082x evaluation kit z8f08200100kit table 124. ordering in formation (continued) part flash kb (bytes) ram kb (bytes) max. speed (mhz) temp ( 0 c) voltage (v) package part number
ps019707-1003 p r e l i m i n a r y ordering information z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 218 part number description zilog part numbers consist of a number of components, as indicated in the following examples: for example, part number z8 f 0821hh020sc is an 8-bit microcontroller product in a 20- pin ssop package, operating with a maximum 20-mhz external clock frequency over a 0oc to +70oc temperature range and built usin g the plastic-standard environmental flow. zilog base products z8 zilog 8-bit microcontroller product f0821 product number hh package 020 speed s temperature c environmental flow packages hh = 20-pin ssop ph = 20-pin pdip sj = 28-pin soic pj = 28-pin pdip speed 020 = 20 mhz temperature s = 0oc to +70oc e = -40oc to +105oc environmental flow c = plastic-standard
ps019707-1003 p r e l i m i n a r y ordering information z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 219 precharacterization product the product represented by this document is newly introduced and zilog has not com- pleted the full characterization of the prod uct. the document states what zilog knows about this product at this time, but additi onal features or nonconformance with some aspects of the document might be found, either by zilog or its customers in the course of further application and charact erization work. in addition, zilog cautions that delivery might be uncertain at times, due to start-up yield issues. zilog, inc. 532 race street san jose, ca 95126 telephone (408) 558-8500 fax 408 558-8300 internet: www.zilog.com document information document number description the document control number that appears in the footer on each page of this document contains unique identifying attributes, as indicated in the following table: customer feedback form the z8 encore! ? product specification if you experience any problems while operating this product, or if you note any inaccura- cies while reading this product specification, please copy and complete this form, then mail or fax it to zilog (see return information , below). we also welcome your sugges- tions! customer information ps product specification 0197 unique document number 07 revision number 1003 month and year published name country company phone address fax city/state/zip e-mail
ps019707-1003 p r e l i m i n a r y ordering information z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 220 product information return information zilog 532 race street san jose, ca 95126 fax: (408) 558-8536 part #, serial #, board fab #, or rev. # software version document number host computer description/type
ps019707-1003 p r e l i m i n a r y ordering information z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 221 problem description or suggestion provide a complete description of th e problem or your suggestion. if yo u are reporting a specific problem, include all steps leading up to the occurrence of the problem. attach additional pages as necessary. ______________________________________________________________________________________ ______________________________________________________________________________________ ______________________________________________________________________________________ ______________________________________________________________________________________ ______________________________________________________________________________________ ______________________________________________________________________________________ ______________________________________________________________________________________ ______________________________________________________________________________________ ______________________________________________________________________________________ ______________________________________________________________________________________ ______________________________________________________________________________________
ps019707-1003 p r e l i m i n a r y index z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 222 index symbols # 191 % 191 @ 191 numerics 10-bit adc 4 40-lead plastic dual-inline package 214 a about this manual xvi absolute maximum ratings 171 ac characteristics 175 adc 193 architecture 133 automatic power-down 134 block diagram 134 continuous conversion 135 control register 136 control register definitions 136 data high byte register 137 data low bits register 138 electrical characteristics and timing 178 operation 134 single-shot conversion 134 adcctl register 136 adcdh register 137 adcdl register 138 adcx 193 add 193 add - extended addressing 193 add with carry 193 add with carry - extended addressing 193 additional symbols 191 address space 13 addx 193 all uppercase letters, use of xviii analog signals 10 analog-to-digital converter (adc) 133 and 196 andx 196 arithmetic instructions 193 assembly language programming 188 assembly language syntax 189 b b 191 b 190 baud rate generator, uart 91 bclr 194 binary number suffix 191 bit 194 bit 190 clear 194 manipulation instructions 194 set 194 set or clear 194 swap 194 test and jump 196 test and jump if non-zero 196 test and jump if zero 196 bit jump and test if non-zero 196 bit numbering xviii bit swap 197 bits and similar registers, notation for xvii block diagram 3 block transfer instructions 194 braces xvii brackets xvi brk 196 bset 194 bswap 194 , 197 btj 196 btjnz 196 btjz 196 c call procedure 196 capture mode 74 capture/compare mode 74
ps019707-1003 p r e l i m i n a r y index z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 223 cc 190 ccf 195 characteristics, electrical 171 clear 195 clock phase (spi) 110 clr 195 com 196 compare 74 compare - extended addressing 193 compare mode 74 compare with carry 193 compare with carry - extended addressing 193 complement 196 complement carry flag 194 , 195 condition code 190 continuous conversion (adc) 135 continuous mode 73 control register definition, uart 92 control register, i2c 129 counter modes 73 courier typeface xvi cp 193 cpc 193 cpcx 193 cpu and peripheral overview 4 cpu control instructions 195 cpx 193 customer feedback form 219 customer information 219 d da 190 , 193 data register, i2c 127 dc characteristics 173 debugger, on-chip 153 dec 193 decimal adjust 193 decrement 193 decrement and jump non-zero 196 decrement word 193 decw 193 destination operand 191 device, port availability 37 di 195 direct address 190 disable interrupts 195 djnz 196 dma controller 5 document number description 219 dst 191 e ei 195 electrical characteristics 171 adc 178 flash memory and timing 177 gpio input data sample timing 180 watch-dog timer 178 enable interrupt 195 er 190 extended addressing register 190 external pin reset 33 ez8 cpu features 4 ez8 cpu instruction classes 193 ez8 cpu instruction notation 189 ez8 cpu instruction set 188 ez8 cpu instruction summary 197 f fctl register 145 features, z8 encore! 1 first opcode map 210 flags 191 flags register 191 flash controller 4 option bit address space 150 option bit configuration - reset 150 program memory address 0000h 151 program memory address 0001h 152 flash memory 139 arrrangement 140 byte programming 143 code protection 142
ps019707-1003 p r e l i m i n a r y index z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 224 configurations 139 control register definitions 145 controller bypass 144 electrical characteristics and timing 177 flash control register 145 flash status register 146 frequency high and low byte registers 149 mass erase 144 operation 141 operation timing 141 page erase 144 page select register 147 fps register 147 fstat register 146 g gated mode 74 general-purpose i/o 37 gpio 4 , 37 alternate functions 38 architecture 37 control register definitions 40 input data sample timing 180 interrupts 39 port a-c pull-up enable sub-registers 45 port a-h address registers 40 port a-h alternate fu nction sub-registers 42 port a-h control registers 41 port a-h data direction sub-registers 42 port a-h high drive enable sub-registers 44 port a-h input data registers 46 port a-h output control sub-registers 43 port a-h output data registers 47 port a-h stop mode re covery sub-registers 44 port availability by device 37 port input timing 180 port output timing 181 h h 191 halt 195 halt mode 36 , 195 hexadecimal number prefix/suffix 191 hexadecimal values xvi i i2c 4 10-bit address read transaction 126 10-bit address transaction 124 10-bit addressed slave data transfer format 124 10-bit receive data format 126 7-bit address transaction 123 7-bit address, reading a transaction 125 7-bit addressed slave data transfer format 123 7-bit receive data transfer format 125 baud high and low byte registers 130 , 132 c status register 128 control register definitions 127 controller 121 controller signals 9 interrupts 122 operation 121 sda and scl signals 121 stop and start conditions 122 i2cbrh register 131 , 132 i2cbrl register 131 i2cctl register 129 i2cdata register 128 i2cstat register 128 im 190 immediate data 190 immediate operand prefix 191 inc 193 increment 193 increment word 193 incw 193 indexed 190 indirect address prefix 191 indirect register 190 indirect register pair 190 indirect working register 190 indirect working register pair 190 infrared encoder/decoder (irda) 102 initial uppercase letters, use of xvii instruction set, ez8 cpu 188
ps019707-1003 p r e l i m i n a r y index z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 225 instructions adc 193 adcx 193 add 193 addx 193 and 196 andx 196 arithmetic 193 bclr 194 bit 194 bit manipulation 194 block transfer 194 brk 196 bset 194 bswap 194 , 197 btj 196 btjnz 196 btjz 196 call 196 ccf 194 , 195 clr 195 com 196 cp 193 cpc 193 cpcx 193 cpu control 195 cpx 193 da 193 dec 193 decw 193 di 195 djnz 196 ei 195 halt 195 inc 193 incw 193 iret 196 jp 196 ld 195 ldc 195 ldci 194 , 195 lde 195 ldei 194 ldx 195 lea 195 load 195 logical 196 mult 193 nop 195 or 196 orx 196 pop 195 popx 195 program control 196 push 195 pushx 195 rcf 194 , 195 ret 196 rl 197 rlc 197 rotate and shift 197 rr 197 rrc 197 sbc 194 scf 194 , 195 sra 197 srl 197 srp 195 stop 195 sub 194 subx 194 swap 197 tcm 194 tcmx 194 tm 194 tmx 194 trap 196 watch-dog timer refresh 195 xor 196 xorx 196 instructions, ez8 classes of 193 intended audience xvi interrupt control register 59 interrupt controller 5 , 48 architecture 48 interrupt assertion types 51 interrupt vectors and priority 51 operation 50
ps019707-1003 p r e l i m i n a r y index z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 226 register definitions 52 software interrupt assertion 51 interrupt edge select register 58 interrupt request 0 register 52 interrupt request 1 register 53 interrupt request 2 register 54 interrupt return 196 interrupt vector listing 48 interrupts not acknowledge 122 receive 122 spi 113 transmit 122 uart 89 introduction 1 ir 190 ir 190 irda architecture 102 block diagram 102 control register definitions 106 operation 103 receiving data 104 transmitting data 103 iret 196 irq0 enable high and low bit registers 55 irq1 enable high and low bit registers 56 irq2 enable high and low bit registers 57 irr 190 irr 190 j jp 196 jump, conditional, relative, and relative conditional 196 l ld 195 ldc 195 ldci 194 , 195 lde 195 ldei 194 , 195 ldx 195 lea 195 load 195 load constant 194 load constant to/from program memory 195 load constant with auto-increment addresses 195 load effective address 195 load external data 195 load external data to/fro m data memory and auto- increment addresses 194 load external to/from data memory and auto-incre- ment addresses 195 load instructions 195 load using extended addressing 195 logical and 196 logical and/extended addressing 196 logical exclusive or 196 logical exclusive or/extended addressing 196 logical instructions 196 logical or 196 logical or/extended addressing 196 low power modes 35 lsb and msb, use of the terms xvii m manual conventions xvi manual objectives xvi master interrupt enable 50 master-in, slave-out and-in 109 memory program 14 miso 109 mode capture 74 capture/compare 74 continuous 73 counter 73 gated 74 one-shot 73 pwm 73 modes 74 mosi 109 mult 193
ps019707-1003 p r e l i m i n a r y index z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 227 multiply 193 multiprocessor mode, uart 87 n nop (no operation) 195 not acknowledge interrupt 122 notation b 190 cc 190 da 190 er 190 im 190 ir 190 ir 190 irr 190 irr 190 p 190 r 190 r 190 ra 190 rr 190 rr 190 vector 190 x 190 notational shorthand 190 o ocd architecture 153 auto-baud detector/generator 156 baud rate limits 156 block diagram 153 breakpoints 157 commands 159 control register 163 data format 156 dbg pin to rs-232 interface 154 debug mode 155 debugger break 196 interface 154 serial errors 157 status register 165 timing 182 ocd commands execute instruction (12h) 163 read data memory (0dh) 162 read ocd control register (05h) 161 read ocd revision (00h) 160 read ocd status register (02h) 160 read program counter (07h) 161 read program memory (0bh) 162 read program memory crc (0eh) 163 read register (09h) 161 read runtime counter (03h) 160 step instruction (10h) 163 stuff instruction (11h) 163 write data memory (0ch) 162 write ocd control register (04h) 160 write program counter (06h) 161 write program memory (0ah) 162 write register (08h) 161 on-chip debugger 5 on-chip debugger (ocd) 153 on-chip debugger signals 10 on-chip oscillator 167 one-shot mode 73 opcode map abbreviations 209 cell description 208 first 210 second after 1fh 211 operational description 81 or 196 ordering information 216 orx 196 oscillator signals 10 p p 190 packaging pdip 214 parentheses xvii parentheses/bracket combinations xvii part number description 218 part selection guide 2
ps019707-1003 p r e l i m i n a r y index z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 228 pc 191 pdip 214 peripheral ac and dc el ectrical characteristics 177 phase=0 timing (spi) 111 phase=1 timing (spi) 112 pin characteristics 11 polarity 190 pop 195 pop using extended addressing 195 popx 195 port availability, device 37 port input timing (gpio) 180 port output timing, gpio 181 power supply signals 11 power-down, automatic (adc) 134 power-on and voltage brown-out 177 power-on reset (por) 30 problem description or suggestion 221 product information 220 program control instructions 196 program counter 191 program memory 14 push 195 push using extended addressing 195 pushx 195 pwm mode 73 pxaddr register 40 pxctl register 41 r r 190 r 190 ra register address 190 rcf 194 , 195 receive 10-bit data format (i2c) 126 7-bit data transfer format (i2c) 125 irda data 104 receive interrupt 122 receiving uart data-interrupt-driven method 85 receiving uart data-polled method 85 register 118 , 190 adc control (adcctl) 136 adc data high byte (adcdh) 137 adc data low bits (adcdl) 138 baud low and high byte (i2c) 130 , 132 baud rate high and low byte (spi) 120 control (spi) 115 control, i2c 129 data, spi 114 flash control (fctl) 145 flash high and low byte (ffreqh and fre- eql) 149 flash page select (fps) 147 flash status (fstat) 146 gpio port a-h address (pxaddr) 40 gpio port a-h alternate function sub-registers 42 gpio port a-h control address (pxctl) 41 gpio port a-h data direction sub-registers 42 i2c baud rate high (i2cbrh) 131 , 132 i2c control (i2cctl) 129 i2c data (i2cdata) 128 i2c status 128 i2c status (i2cstat) 128 i2cbaud rate low (i2cbrl) 131 mode, spi 118 ocd control 163 ocd status 165 spi baud rate high byte (spibrh) 120 spi baud rate low byte (spibrl) 120 spi control (spictl) 115 spi data (spidata) 115 spi status (spistat) 117 status, i2c 128 status, spi 116 uartx baud rate high byte (uxbrh) 99 uartx baud rate low byte (uxbrl) 99 uartx control 0 (uxctl0) 95 , 98 uartx control 1 (uxctl1) 97 uartx receive data (uxrxd) 93 uartx status 0 (uxstat0) 93 uartx status 1 (uxstat1) 95 uartx transmit data (uxtxd) 92 watch-dog timer control (wdtctl) 78 watch-dog timer reload high byte (wdth) 80
ps019707-1003 p r e l i m i n a r y index z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 229 watch-dog timer reload low byte (wdtl) 80 watch-dog timer reload upper byte (wdtu) 79 register file 13 register file address map 16 register pair 190 register pointer 191 reset and stop mode characteristics 29 and stop mode recovery 29 carry flag 194 controller 5 sources 30 ret 196 return 196 return information 220 rl 197 rlc 197 rotate and shift instuctions 197 rotate left 197 rotate left through carry 197 rotate right 197 rotate right through carry 197 rp 191 rr 190 , 197 rr 190 rrc 197 s safeguards xviii sbc 194 scf 194 , 195 sck 109 sda and scl (irda) signals 121 second opcode map after 1fh 211 serial clock 109 serial peripheral interface (spi) 107 set and clear, use of the words xvii set carry flag 194 , 195 set register pointer 195 shift right arithmatic 197 shift right logical 197 signal descriptions 9 single-sho conversion (adc) 134 sio 5 slave data transfer formats (i2c) 124 slave select 110 software trap 196 source operand 191 sp 191 spi architecture 107 baud rate generator 114 baud rate high and low byte register 120 clock phase 110 configured as slave 108 control register 115 control register definitions 114 data register 114 error detection 113 interrupts 113 mode fault error 113 mode register 118 multi-master operation 112 operation 108 overrun error 113 signals 109 single master, multiple slave system 108 single master,single slave system 107 status register 116 timing, phase = 0 111 timing, phase=1 112 spi controller signals 9 spi mode (spimode) 118 spibrh register 120 spibrl register 120 spictl register 115 spidata register 115 spimode register 118 spistat register 117 sra 197 src 191 srl 197 srp 195 ss, spi signal 109 stack pointer 191 status register, i2c 128 stop 195
ps019707-1003 p r e l i m i n a r y index z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 230 stop mode 35 , 195 stop mode recovery sources 33 using a gpio port pin transition 34 using watch-dog timer time-out 33 sub 194 subtract 194 subtract - extended addressing 194 subtract with carry 194 subtract with carry - extended addressing 194 subx 194 swap 197 swap nibbles 197 symbols, additional 191 system and core resets 30 t tcm 194 tcmx 194 test complement under mask 194 test complement under mask - extended addressing 194 test under mask 194 test under mask - extended addressing 194 timer signals 10 timers 5 , 60 architecture 60 block diagram 61 capture mode 65 , 74 capture/compare mode 68 , 74 compare mode 66 , 74 continuous mode 62 , 73 counter mode 63 counter modes 73 gated mode 67 , 74 one-shot mode 61 , 73 operating mode 61 pwm mode 64 , 73 reading the timer count values 69 reload high and low byte registers 70 timer control register definitions 69 timer output signal operation 69 timers 0-3 control registers 73 high and low byte registers 69 , 72 tm 194 tmx 194 tools, hardware and software 217 trademarks xviii transmit irda data 103 transmit interrupt 122 transmitting uart data-polled method 83 transmitting uart dat-interrupt-driven method 84 trap 196 u uart 4 architecture 81 asynchronous data form at without/with parity 83 baud rate generator 91 baud rates table 100 control register definitions 92 controller signals 9 data format 82 interrupts 89 multiprocessor mode 87 receiving data using interrupt-driven method 85 receiving data using the polled method 85 transmitting data usin the interrupt-driven method 84 transmitting data using the polled method 83 x baud rate high and low registers 99 x control 0 and control 1 registers 95 x status 0 and status 1 registers 93 , 95 uxbrh register 99 uxbrl register 99 uxctl0 register 95 , 98 uxctl1 register 97 uxrxd register 93 uxstat0 register 93 uxstat1 register 95 uxtxd register 92
ps019707-1003 p r e l i m i n a r y index z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 231 v vector 190 voltage brown-out reset (vbr) 31 w watch-dog timer approximate time-out delay 76 approximate time-out delays 75 cntl 32 control register 78 electrical characteristics and timing 178 interrupt in noromal operation 76 interrupt in stop mode 76 operation 75 refresh 76 , 195 reload unlock sequence 77 reload upper, high and low registers 79 reset 32 reset in normal operation 77 reset in stop mode 77 time-out response 76 wdtctl register 78 wdth register 80 wdtl register 80 working register 190 working register pair 190 wtdu register 79 x x 190 xor 196 xorx 196 z z8 encore! block diagram 3 features 1 introduction 1 part selection guide 2
ps019707-1003 p r e l i m i n a r y index z8f082x/z8f081x/z8f042x/z8f041x z8 encore! ? 232

▲Up To Search▲

Price & Availability of Z8F0811

	To Download Z8F0811 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .